From: Bin Meng bmeng@tinylab.org Sent: Monday, June 12, 2023 3:36 PM To: u-boot@lists.denx.de Cc: Andre Przywara andre.przywara@arm.com; Anup Patel apatel@ventanamicro.com; Jonas Schwöbel jonasschwoebel@yahoo.de; Kautuk Consul kconsul@ventanamicro.com; Leo Yu-Chi Liang(梁育齊) ycliang@andestech.com; Michael Walle michael@walle.cc; Michal Simek michal.simek@amd.com; Nikita Shubin n.shubin@yadro.com; Rick Jian-Zhi Chen(陳建志) rick@andestech.com; Sean Anderson seanga2@gmail.com; Sergei Antonov saproj@gmail.com; Simon Glass sjg@chromium.org; Stefan Herbrechtsmeier stefan.herbrechtsmeier@weidmueller.com; Svyatoslav Ryhel clamor95@gmail.com; Tianrui Wei tianrui-wei@outlook.com; William Zhang william.zhang@broadcom.com; Yanhong Wang yanhong.wang@starfivetech.com; Peter Yu-Chien Lin(林宇謙) peterlin@andestech.com Subject: [PATCH 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng bmeng@tinylab.org
MAINTAINERS | 2 +- arch/riscv/Kconfig | 8 ++++---- arch/riscv/cpu/fu540/Kconfig | 2 +- arch/riscv/cpu/fu740/Kconfig | 2 +- arch/riscv/cpu/generic/Kconfig | 4 ++-- arch/riscv/cpu/jh7110/Kconfig | 2 +- arch/riscv/include/asm/global_data.h | 4 ++-- arch/riscv/include/asm/syscon.h | 2 +- arch/riscv/lib/Makefile | 2 +- .../lib/{sifive_clint.c => aclint_ipi.c} | 16 +++++++-------- board/openpiton/riscv64/Kconfig | 2 +- board/sipeed/maix/Kconfig | 2 +- drivers/timer/Makefile | 2 +- ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +++++++++---------- 14 files changed, 35 insertions(+), 35 deletions(-) rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (73%) rename drivers/timer/{sifive_clint_timer.c => riscv_aclint_timer.c} (75%)
Reviewed-by: Rick Chen rick@andestech.com