As the migration deadline has passed, require that DM_PCI be used.
Signed-off-by: Tom Rini trini@konsulko.com --- .azure-pipelines.yml | 16 - .gitlab-ci.yml | 28 -- Makefile | 1 - drivers/pci/Kconfig | 9 +- drivers/pci/Makefile | 4 - drivers/pci/pci.c | 588 ------------------------------------- drivers/pci/pci_auto_old.c | 387 ------------------------ 7 files changed, 5 insertions(+), 1028 deletions(-) delete mode 100644 drivers/pci/pci.c delete mode 100644 drivers/pci/pci_auto_old.c
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 8a567832ddac..438139660219 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -217,22 +217,6 @@ jobs: qemu_mips64el: TEST_PY_BD: "qemu_mips64el" TEST_PY_TEST_SPEC: "not sleep" - qemu_malta: - TEST_PY_BD: "malta" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" - qemu_maltael: - TEST_PY_BD: "maltael" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" - qemu_malta64: - TEST_PY_BD: "malta64" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" - qemu_malta64el: - TEST_PY_BD: "malta64el" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" qemu_ppce500: TEST_PY_BD: "qemu-ppce500" TEST_PY_TEST_SPEC: "not sleep" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index bff487404f30..5bf6f151b4fc 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -249,34 +249,6 @@ qemu_mips64el test.py: TEST_PY_TEST_SPEC: "not sleep" <<: *buildman_and_testpy_dfn
-qemu_malta test.py: - variables: - TEST_PY_BD: "malta" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu_maltael test.py: - variables: - TEST_PY_BD: "maltael" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu_malta64 test.py: - variables: - TEST_PY_BD: "malta64" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu_malta64el test.py: - variables: - TEST_PY_BD: "malta64el" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - qemu-ppce500 test.py: variables: TEST_PY_BD: "qemu-ppce500" diff --git a/Makefile b/Makefile index 559594fe1d8f..fea578a639d7 100644 --- a/Makefile +++ b/Makefile @@ -1088,7 +1088,6 @@ ifneq ($(CONFIG_DM),y) endif $(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\ USB,v2019.07,$(CONFIG_USB)) - $(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI)) $(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\ $(CONFIG_LCD)$(CONFIG_VIDEO)) $(call deprecated,CONFIG_DM_SPI_FLASH,SPI flash,v2019.07,\ diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index d5b6018b3d41..7286d31438ff 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -1,22 +1,23 @@ menuconfig PCI bool "PCI support" + depends on DM default y if PPC + select DM_PCI help Enable support for PCI (Peripheral Interconnect Bus), a type of bus used on some devices to allow the CPU to communicate with its peripherals.
-if PCI - config DM_PCI - bool "Enable driver model for PCI" - depends on DM + bool help Use driver model for PCI. Driver model is the new method for orgnising devices in U-Boot. For PCI, driver model keeps track of available PCI devices, allows scanning of PCI buses and provides device configuration support.
+if PCI + config DM_PCI_COMPAT bool "Enable compatible functions for PCI" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 1f741786a07a..b04d420f996c 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -3,16 +3,12 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifneq ($(CONFIG_DM_PCI),) obj-$(CONFIG_DM_VIDEO) += pci_rom.o obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o obj-$(CONFIG_X86) += pci_x86.o pci_rom.o -else -obj-$(CONFIG_PCI) += pci.o pci_auto_old.o -endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c deleted file mode 100644 index d8f9239523cd..000000000000 --- a/drivers/pci/pci.c +++ /dev/null @@ -1,588 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel aheppel@sysgo.de - * - * (C) Copyright 2002, 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * Old PCI routines - * - * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI - * and change pci-uclass.c. - */ - -#include <common.h> -#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -#include <command.h> -#include <env.h> -#include <errno.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define PCI_HOSE_OP(rw, size, type) \ -int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, \ - int offset, type value) \ -{ \ - return hose->rw##_##size(hose, dev, offset, value); \ -} - -PCI_HOSE_OP(read, byte, u8 *) -PCI_HOSE_OP(read, word, u16 *) -PCI_HOSE_OP(read, dword, u32 *) -PCI_HOSE_OP(write, byte, u8) -PCI_HOSE_OP(write, word, u16) -PCI_HOSE_OP(write, dword, u32) - -#define PCI_OP(rw, size, type, error_code) \ -int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ -{ \ - struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ - \ - if (!hose) \ - { \ - error_code; \ - return -1; \ - } \ - \ - return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ -} - -PCI_OP(read, byte, u8 *, *value = 0xff) -PCI_OP(read, word, u16 *, *value = 0xffff) -PCI_OP(read, dword, u32 *, *value = 0xffffffff) -PCI_OP(write, byte, u8, ) -PCI_OP(write, word, u16, ) -PCI_OP(write, dword, u32, ) - -#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ -int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ - pci_dev_t dev, \ - int offset, type val) \ -{ \ - u32 val32; \ - \ - if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ - *val = -1; \ - return -1; \ - } \ - \ - *val = (val32 >> ((offset & (int)off_mask) * 8)); \ - \ - return 0; \ -} - -#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ -int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ - pci_dev_t dev, \ - int offset, type val) \ -{ \ - u32 val32, mask, ldata, shift; \ - \ - if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ - return -1; \ - \ - shift = ((offset & (int)off_mask) * 8); \ - ldata = (((unsigned long)val) & val_mask) << shift; \ - mask = val_mask << shift; \ - val32 = (val32 & ~mask) | ldata; \ - \ - if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ - return -1; \ - \ - return 0; \ -} - -PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) -PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) -PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) -PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) - -/* - * - */ - -static struct pci_controller* hose_head; - -struct pci_controller *pci_get_hose_head(void) -{ - if (gd->hose) - return gd->hose; - - return hose_head; -} - -void pci_register_hose(struct pci_controller* hose) -{ - struct pci_controller **phose = &hose_head; - - while(*phose) - phose = &(*phose)->next; - - hose->next = NULL; - - *phose = hose; -} - -struct pci_controller *pci_bus_to_hose(int bus) -{ - struct pci_controller *hose; - - for (hose = pci_get_hose_head(); hose; hose = hose->next) { - if (bus >= hose->first_busno && bus <= hose->last_busno) - return hose; - } - - printf("pci_bus_to_hose() failed\n"); - return NULL; -} - -struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) -{ - struct pci_controller *hose; - - for (hose = pci_get_hose_head(); hose; hose = hose->next) { - if (hose->cfg_addr == cfg_addr) - return hose; - } - - return NULL; -} - -int pci_last_busno(void) -{ - struct pci_controller *hose = pci_get_hose_head(); - - if (!hose) - return -1; - - while (hose->next) - hose = hose->next; - - return hose->last_busno; -} - -pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) -{ - struct pci_controller * hose; - pci_dev_t bdf; - int bus; - - for (hose = pci_get_hose_head(); hose; hose = hose->next) { - for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { - bdf = pci_hose_find_devices(hose, bus, ids, &index); - if (bdf != -1) - return bdf; - } - } - - return -1; -} - -static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, - ulong io, pci_addr_t mem, ulong command) -{ - u32 bar_response; - unsigned int old_command; - pci_addr_t bar_value; - pci_size_t bar_size; - unsigned char pin; - int bar, found_mem64; - - debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, - (u64)mem, command); - - pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); - - for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { - pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); - pci_hose_read_config_dword(hose, dev, bar, &bar_response); - - if (!bar_response) - continue; - - found_mem64 = 0; - - /* Check the BAR type and set our address mask */ - if (bar_response & PCI_BASE_ADDRESS_SPACE) { - bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; - /* round up region base address to a multiple of size */ - io = ((io - 1) | (bar_size - 1)) + 1; - bar_value = io; - /* compute new region base address */ - io = io + bar_size; - } else { - if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == - PCI_BASE_ADDRESS_MEM_TYPE_64) { - u32 bar_response_upper; - u64 bar64; - pci_hose_write_config_dword(hose, dev, bar + 4, - 0xffffffff); - pci_hose_read_config_dword(hose, dev, bar + 4, - &bar_response_upper); - - bar64 = ((u64)bar_response_upper << 32) | bar_response; - - bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; - found_mem64 = 1; - } else { - bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); - } - - /* round up region base address to multiple of size */ - mem = ((mem - 1) | (bar_size - 1)) + 1; - bar_value = mem; - /* compute new region base address */ - mem = mem + bar_size; - } - - /* Write it out and update our limit */ - pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); - - if (found_mem64) { - bar += 4; -#ifdef CONFIG_SYS_PCI_64BIT - pci_hose_write_config_dword(hose, dev, bar, - (u32)(bar_value >> 32)); -#else - pci_hose_write_config_dword(hose, dev, bar, 0x00000000); -#endif - } - } - - /* Configure Cache Line Size Register */ - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* Configure Latency Timer */ - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - - /* Disable interrupt line, if device says it wants to use interrupts */ - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); - if (pin != 0) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, - PCI_INTERRUPT_LINE_DISABLE); - } - - pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); - pci_hose_write_config_dword(hose, dev, PCI_COMMAND, - (old_command & 0xffff0000) | command); - - return 0; -} - -/* - * - */ - -struct pci_config_table *pci_find_config(struct pci_controller *hose, - unsigned short class, - unsigned int vendor, - unsigned int device, - unsigned int bus, - unsigned int dev, - unsigned int func) -{ - struct pci_config_table *table; - - for (table = hose->config_table; table && table->vendor; table++) { - if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && - (table->device == PCI_ANY_ID || table->device == device) && - (table->class == PCI_ANY_ID || table->class == class) && - (table->bus == PCI_ANY_ID || table->bus == bus) && - (table->dev == PCI_ANY_ID || table->dev == dev) && - (table->func == PCI_ANY_ID || table->func == func)) { - return table; - } - } - - return NULL; -} - -void pci_cfgfunc_config_device(struct pci_controller *hose, - pci_dev_t dev, - struct pci_config_table *entry) -{ - pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], - entry->priv[2]); -} - -void pci_cfgfunc_do_nothing(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ -} - -/* - * HJF: Changed this to return int. I think this is required - * to get the correct result when scanning bridges - */ -extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); - -#ifdef CONFIG_PCI_SCAN_SHOW -__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) -{ - if (dev == PCI_BDF(hose->first_busno, 0, 0)) - return 0; - - return 1; -} -#endif /* CONFIG_PCI_SCAN_SHOW */ - -int pci_hose_scan_bus(struct pci_controller *hose, int bus) -{ - unsigned int sub_bus, found_multi = 0; - unsigned short vendor, device, class; - unsigned char header_type; -#ifndef CONFIG_PCI_PNP - struct pci_config_table *cfg; -#endif - pci_dev_t dev; -#ifdef CONFIG_PCI_SCAN_SHOW - static int indent = 0; -#endif - - sub_bus = bus; - - for (dev = PCI_BDF(bus,0,0); - dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); - dev += PCI_BDF(0, 0, 1)) { - - if (pci_skip_dev(hose, dev)) - continue; - - if (PCI_FUNC(dev) && !found_multi) - continue; - - pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); - - pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); - - if (vendor == 0xffff || vendor == 0x0000) - continue; - - if (!PCI_FUNC(dev)) - found_multi = header_type & 0x80; - - debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", - PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); - - pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); - pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); - -#ifdef CONFIG_PCI_FIXUP_DEV - board_pci_fixup_dev(hose, dev, vendor, device, class); -#endif - -#ifdef CONFIG_PCI_SCAN_SHOW - indent++; - - /* Print leading space, including bus indentation */ - printf("%*c", indent + 1, ' '); - - if (pci_print_dev(hose, dev)) { - printf("%02x:%02x.%-*x - %04x:%04x - %s\n", - PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), - vendor, device, pci_class_str(class >> 8)); - } -#endif - -#ifdef CONFIG_PCI_PNP - sub_bus = max((unsigned int)pciauto_config_device(hose, dev), - sub_bus); -#else - cfg = pci_find_config(hose, class, vendor, device, - PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); - if (cfg) { - cfg->config_device(hose, dev, cfg); - sub_bus = max(sub_bus, - (unsigned int)hose->current_busno); - } -#endif - -#ifdef CONFIG_PCI_SCAN_SHOW - indent--; -#endif - - if (hose->fixup_irq) - hose->fixup_irq(hose, dev); - } - - return sub_bus; -} - -int pci_hose_scan(struct pci_controller *hose) -{ -#if defined(CONFIG_PCI_BOOTDELAY) - char *s; - int i; - - if (!gd->pcidelay_done) { - /* wait "pcidelay" ms (if defined)... */ - s = env_get("pcidelay"); - if (s) { - int val = simple_strtoul(s, NULL, 10); - for (i = 0; i < val; i++) - udelay(1000); - } - gd->pcidelay_done = 1; - } -#endif /* CONFIG_PCI_BOOTDELAY */ - -#ifdef CONFIG_PCI_SCAN_SHOW - puts("PCI:\n"); -#endif - - /* - * Start scan at current_busno. - * PCIe will start scan at first_busno+1. - */ - /* For legacy support, ensure current >= first */ - if (hose->first_busno > hose->current_busno) - hose->current_busno = hose->first_busno; -#ifdef CONFIG_PCI_PNP - pciauto_config_init(hose); -#endif - return pci_hose_scan_bus(hose, hose->current_busno); -} - -int pci_init(void) -{ - hose_head = NULL; - - /* allow env to disable pci init/enum */ - if (env_get("pcidisable") != NULL) - return 0; - - /* now call board specific pci_init()... */ - pci_init_board(); - - return 0; -} - -/* Returns the address of the requested capability structure within the - * device's PCI configuration space or 0 in case the device does not - * support it. - * */ -int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, - int cap) -{ - int pos; - u8 hdr_type; - - pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); - - pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); - - if (pos) - pos = pci_find_cap(hose, dev, pos, cap); - - return pos; -} - -/* Find the header pointer to the Capabilities*/ -int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, - u8 hdr_type) -{ - u16 status; - - pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); - - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - switch (hdr_type) { - case PCI_HEADER_TYPE_NORMAL: - case PCI_HEADER_TYPE_BRIDGE: - return PCI_CAPABILITY_LIST; - case PCI_HEADER_TYPE_CARDBUS: - return PCI_CB_CAPABILITY_LIST; - default: - return 0; - } -} - -int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) -{ - int ttl = PCI_FIND_CAP_TTL; - u8 id; - u8 next_pos; - - while (ttl--) { - pci_hose_read_config_byte(hose, dev, pos, &next_pos); - if (next_pos < CAP_START_POS) - break; - next_pos &= ~3; - pos = (int) next_pos; - pci_hose_read_config_byte(hose, dev, - pos + PCI_CAP_LIST_ID, &id); - if (id == 0xff) - break; - if (id == cap) - return pos; - pos += PCI_CAP_LIST_NEXT; - } - return 0; -} - -/** - * pci_find_next_ext_capability - Find an extended capability - * - * Returns the address of the next matching extended capability structure - * within the device's PCI configuration space or 0 if the device does - * not support it. Some capabilities can occur several times, e.g., the - * vendor-specific capability, and this provides a way to find them all. - */ -int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev, - int start, int cap) -{ - u32 header; - int ttl, pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos = start; - - pci_hose_read_config_dword(hose, dev, pos, &header); - if (header == 0xffffffff || header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos != start) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - pci_hose_read_config_dword(hose, dev, pos, &header); - if (header == 0xffffffff || header == 0) - break; - } - - return 0; -} - -/** - * pci_hose_find_ext_capability - Find an extended capability - * - * Returns the address of the requested extended capability structure - * within the device's PCI configuration space or 0 if the device does - * not support it. - */ -int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, - int cap) -{ - return pci_find_next_ext_capability(hose, dev, 0, cap); -} diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c deleted file mode 100644 index c56ff53c4f9f..000000000000 --- a/drivers/pci/pci_auto_old.c +++ /dev/null @@ -1,387 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * PCI autoconfiguration library (legacy version, do not change) - * - * Author: Matt Porter mporter@mvista.com - * - * Copyright 2000 MontaVista Software Inc. - */ - -#include <common.h> -#include <errno.h> -#include <log.h> -#include <pci.h> - -/* - * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI - * and change pci_auto.c. - */ - -/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ -#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 -#endif - -/* - * - */ - -void pciauto_setup_device(struct pci_controller *hose, - pci_dev_t dev, int bars_num, - struct pci_region *mem, - struct pci_region *prefetch, - struct pci_region *io) -{ - u32 bar_response; - pci_size_t bar_size; - u16 cmdstat = 0; - int bar, bar_nr = 0; - u8 header_type; - int rom_addr; - pci_addr_t bar_value; - struct pci_region *bar_res; - int found_mem64 = 0; - u16 class; - - pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); - cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; - - for (bar = PCI_BASE_ADDRESS_0; - bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { - /* Tickle the BAR and get the response */ - pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); - pci_hose_read_config_dword(hose, dev, bar, &bar_response); - - /* If BAR is not implemented go to the next BAR */ - if (!bar_response) - continue; - - found_mem64 = 0; - - /* Check the BAR type and set our address mask */ - if (bar_response & PCI_BASE_ADDRESS_SPACE) { - bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) - & 0xffff) + 1; - bar_res = io; - - debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", - bar_nr, (unsigned long long)bar_size); - } else { - if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == - PCI_BASE_ADDRESS_MEM_TYPE_64) { - u32 bar_response_upper; - u64 bar64; - - pci_hose_write_config_dword(hose, dev, bar + 4, - 0xffffffff); - pci_hose_read_config_dword(hose, dev, bar + 4, - &bar_response_upper); - - bar64 = ((u64)bar_response_upper << 32) | bar_response; - - bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; - found_mem64 = 1; - } else { - bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); - } - if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) - bar_res = prefetch; - else - bar_res = mem; - - debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", - bar_nr, bar_res == prefetch ? "Prf" : "Mem", - (unsigned long long)bar_size); - } - - if (pciauto_region_allocate(bar_res, bar_size, - &bar_value, found_mem64) == 0) { - /* Write it out and update our limit */ - pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); - - if (found_mem64) { - bar += 4; -#ifdef CONFIG_SYS_PCI_64BIT - pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); -#else - /* - * If we are a 64-bit decoder then increment to the - * upper 32 bits of the bar and force it to locate - * in the lower 4GB of memory. - */ - pci_hose_write_config_dword(hose, dev, bar, 0x00000000); -#endif - } - - } - cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? - PCI_COMMAND_IO : PCI_COMMAND_MEMORY; - - debug("\n"); - - bar_nr++; - } - - /* Configure the expansion ROM address */ - pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); - header_type &= 0x7f; - if (header_type != PCI_HEADER_TYPE_CARDBUS) { - rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? - PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; - pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe); - pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response); - if (bar_response) { - bar_size = -(bar_response & ~1); - debug("PCI Autoconfig: ROM, size=%#x, ", - (unsigned int)bar_size); - if (pciauto_region_allocate(mem, bar_size, - &bar_value, false) == 0) { - pci_hose_write_config_dword(hose, dev, rom_addr, - bar_value); - } - cmdstat |= PCI_COMMAND_MEMORY; - debug("\n"); - } - } - - /* PCI_COMMAND_IO must be set for VGA device */ - pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); - if (class == PCI_CLASS_DISPLAY_VGA) - cmdstat |= PCI_COMMAND_IO; - - pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, - CONFIG_SYS_PCI_CACHE_LINE_SIZE); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); -} - -void pciauto_prescan_setup_bridge(struct pci_controller *hose, - pci_dev_t dev, int sub_bus) -{ - struct pci_region *pci_mem; - struct pci_region *pci_prefetch; - struct pci_region *pci_io; - u16 cmdstat, prefechable_64; - - pci_mem = hose->pci_mem; - pci_prefetch = hose->pci_prefetch; - pci_io = hose->pci_io; - - pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); - pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, - &prefechable_64); - prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; - - /* Configure bus number registers */ - pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, - PCI_BUS(dev) - hose->first_busno); - pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, - sub_bus - hose->first_busno); - pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); - - if (pci_mem) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_mem, 0x100000); - - /* Set up memory and I/O filter limits, assume 32-bit I/O space */ - pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, - (pci_mem->bus_lower & 0xfff00000) >> 16); - - cmdstat |= PCI_COMMAND_MEMORY; - } - - if (pci_prefetch) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_prefetch, 0x100000); - - /* Set up memory and I/O filter limits, assume 32-bit I/O space */ - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, - (pci_prefetch->bus_lower & 0xfff00000) >> 16); - if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) -#ifdef CONFIG_SYS_PCI_64BIT - pci_hose_write_config_dword(hose, dev, - PCI_PREF_BASE_UPPER32, - pci_prefetch->bus_lower >> 32); -#else - pci_hose_write_config_dword(hose, dev, - PCI_PREF_BASE_UPPER32, - 0x0); -#endif - - cmdstat |= PCI_COMMAND_MEMORY; - } else { - /* We don't support prefetchable memory for now, so disable */ - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); - if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { - pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0); - pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0); - } - } - - if (pci_io) { - /* Round I/O allocator to 4KB boundary */ - pciauto_region_align(pci_io, 0x1000); - - pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, - (pci_io->bus_lower & 0x0000f000) >> 8); - pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, - (pci_io->bus_lower & 0xffff0000) >> 16); - - cmdstat |= PCI_COMMAND_IO; - } - - /* Enable memory and I/O accesses, enable bus master */ - pci_hose_write_config_word(hose, dev, PCI_COMMAND, - cmdstat | PCI_COMMAND_MASTER); -} - -void pciauto_postscan_setup_bridge(struct pci_controller *hose, - pci_dev_t dev, int sub_bus) -{ - struct pci_region *pci_mem; - struct pci_region *pci_prefetch; - struct pci_region *pci_io; - - pci_mem = hose->pci_mem; - pci_prefetch = hose->pci_prefetch; - pci_io = hose->pci_io; - - /* Configure bus number registers */ - pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, - sub_bus - hose->first_busno); - - if (pci_mem) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_mem, 0x100000); - - pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, - (pci_mem->bus_lower - 1) >> 16); - } - - if (pci_prefetch) { - u16 prefechable_64; - - pci_hose_read_config_word(hose, dev, - PCI_PREF_MEMORY_LIMIT, - &prefechable_64); - prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; - - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_prefetch, 0x100000); - - pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, - (pci_prefetch->bus_lower - 1) >> 16); - if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) -#ifdef CONFIG_SYS_PCI_64BIT - pci_hose_write_config_dword(hose, dev, - PCI_PREF_LIMIT_UPPER32, - (pci_prefetch->bus_lower - 1) >> 32); -#else - pci_hose_write_config_dword(hose, dev, - PCI_PREF_LIMIT_UPPER32, - 0x0); -#endif - } - - if (pci_io) { - /* Round I/O allocator to 4KB boundary */ - pciauto_region_align(pci_io, 0x1000); - - pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, - ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); - pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, - ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); - } -} - - -/* - * HJF: Changed this to return int. I think this is required - * to get the correct result when scanning bridges - */ -int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) -{ - struct pci_region *pci_mem; - struct pci_region *pci_prefetch; - struct pci_region *pci_io; - unsigned int sub_bus = PCI_BUS(dev); - unsigned short class; - int n; - - pci_mem = hose->pci_mem; - pci_prefetch = hose->pci_prefetch; - pci_io = hose->pci_io; - - pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); - - switch (class) { - case PCI_CLASS_BRIDGE_PCI: - debug("PCI Autoconfig: Found P2P bridge, device %d\n", - PCI_DEV(dev)); - - pciauto_setup_device(hose, dev, 2, pci_mem, - pci_prefetch, pci_io); - - /* Passing in current_busno allows for sibling P2P bridges */ - hose->current_busno++; - pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); - /* - * need to figure out if this is a subordinate bridge on the bus - * to be able to properly set the pri/sec/sub bridge registers. - */ - n = pci_hose_scan_bus(hose, hose->current_busno); - - /* figure out the deepest we've gone for this leg */ - sub_bus = max((unsigned int)n, sub_bus); - pciauto_postscan_setup_bridge(hose, dev, sub_bus); - - sub_bus = hose->current_busno; - break; - - case PCI_CLASS_BRIDGE_CARDBUS: - /* - * just do a minimal setup of the bridge, - * let the OS take care of the rest - */ - pciauto_setup_device(hose, dev, 0, pci_mem, - pci_prefetch, pci_io); - - debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", - PCI_DEV(dev)); - - hose->current_busno++; - break; - -#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) - case PCI_CLASS_BRIDGE_OTHER: - debug("PCI Autoconfig: Skipping bridge device %d\n", - PCI_DEV(dev)); - break; -#endif -#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \ - !defined(CONFIG_TARGET_CADDY2) - case PCI_CLASS_BRIDGE_OTHER: - /* - * The host/PCI bridge 1 seems broken in 8349 - it presents - * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ - * device claiming resources io/mem/irq.. we only allow for - * the PIMMR window to be allocated (BAR0 - 1MB size) - */ - debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); - pciauto_setup_device(hose, dev, 0, hose->pci_mem, - hose->pci_prefetch, hose->pci_io); - break; -#endif - - case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ - debug("PCI AutoConfig: Found PowerPC device\n"); - - default: - pciauto_setup_device(hose, dev, 6, pci_mem, - pci_prefetch, pci_io); - break; - } - - return sub_bus; -}