The default NAND flash timings are very conservative. This patch assigns the timings reccomended in the recent linux kernel patch [1] from Sekhar Nori. The speedup, as reported in that patch, is 5.3x for reads.
[1] http://www.spinics.net/lists/arm-kernel/msg100278.html
Signed-off-by: Ben Gardiner bengardiner@nanometrics.ca CC: Sekhar Nori nsekhar@ti.com To: Sudhakar Rajashekhara sudhakar.raj@ti.com
---
V2: * Rebased to b69b02b92f59330be9d662110e202cfd3503eafa of u-boot-ti/master
--- board/davinci/da8xxevm/da850evm.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index f84adb9..0eb9e29 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -24,6 +24,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> +#include <asm/arch/emif_defs.h> #include <asm/io.h> #include "../common/misc.h" #include "common.h" @@ -98,6 +99,23 @@ int board_init(void) irq_init(); #endif
+ +#ifdef CONFIG_NAND_DAVINCI + /* + * NAND CS setup - cycle counts based on da850evm NAND timings in the + * Linux kernel @ 25MHz EMIFA + */ + writel((DAVINCI_ABCR_WSETUP(0) | + DAVINCI_ABCR_WSTROBE(0) | + DAVINCI_ABCR_WHOLD(0) | + DAVINCI_ABCR_RSETUP(0) | + DAVINCI_ABCR_RSTROBE(1) | + DAVINCI_ABCR_RHOLD(0) | + DAVINCI_ABCR_TA(0) | + DAVINCI_ABCR_ASIZE_8BIT), + &davinci_emif_regs->ab2cr); /* CS3 */ +#endif + /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;