Re: [PATCH 12/16] ram: stm32mp1: add support of STM32MP13x

HI Patrick

On 5/6/22 16:06, Patrick Delaunay wrote:

Add support for new compatible "st,stm32mp13-ddr" to manage the DDR sub system (Controller and PHY) in STM32MP13x SOC:

• only one AXI port
• support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)

The STM32MP15x SOC have 2 AXI ports and 32 bits support.

Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com

.../memory-controllers/st,stm32mp1-ddr.txt | 49 +++++++++++++++---- drivers/ram/stm32mp1/stm32mp1_ram.c | 28 +++++++---- 2 files changed, 57 insertions(+), 20 deletions(-)

diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt index 926e3e83b3..e6ea8d0ef5 100644 --- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt +++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt @@ -3,7 +3,8 @@ ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)

---

Required properties:

-- compatible : Should be "st,stm32mp1-ddr" +- compatible : Should be "st,stm32mp1-ddr" for STM32MP15x

•   Should be "st,stm32mp13-ddr" for STM32MP13x
  

• reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
• clocks : controller clocks handle
• clock-names : associated controller clock names

@@ -13,6 +14,8 @@ Required properties: the next attributes are DDR parameters, they are generated by DDR tools included in STM32 Cube tool

+They are required only in SPL, when TFABOOT is not activated.

info attributes:

• st,mem-name : name for DDR configuration, simple string for information

@@ -24,7 +27,7 @@ controlleur attributes:

• st,ctl-reg : controleur values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
• for STM32MP15x: 25 values are requested in this order

• for STM32MP15x and STM32MP13x: 25 values are requested in this order MSTR MRCTRL0 MRCTRL1

@@ -53,7 +56,7 @@ controlleur attributes:

• st,ctl-timing : controleur values depending of frequency and timing parameter of DDR
• for STM32MP15x: 12 values are requested in this order

• for STM32MP15x and STM32MP13x: 12 values are requested in this order RFSHTMG DRAMTMG0 DRAMTMG1

@@ -68,7 +71,7 @@ controlleur attributes: ODTCFG

• st,ctl-map : controleur values depending of address mapping
• for STM32MP15x: 9 values are requested in this order

• for STM32MP15x and STM32MP13x: 9 values are requested in this order ADDRMAP1 ADDRMAP2 ADDRMAP3

@@ -99,6 +102,19 @@ controlleur attributes: PCFGWQOS0_1 PCFGWQOS1_1

• for STM32MP13x: 11 values are requested in this order

• SCHED
  

• SCHED1
  

• PERFHPR1
  

• PERFLPR1
  

• PERFWR1
  

• PCFGR_0
  

• PCFGW_0
  

• PCFGQOS0_0
  

• PCFGQOS1_0
  

• PCFGWQOS0_0
  

• PCFGWQOS1_0
  

phyc attributes:

• st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)

@@ -115,8 +131,19 @@ phyc attributes: DX2GCR DX3GCR

• for STM32MP13x: 9 values are requested in this order

• PGCR
  

• ACIOCR
  

• DXCCR
  

• DSGCR
  

• DCR
  

• ODTCR
  

• ZQ0CR1
  

• DX0GCR
  

• DX1GCR
  

• st,phy-timing : phy values depending of frequency and timing parameter of DDR
• for STM32MP15x: 10 values are requested in this order

• for STM32MP15x and STM32MP13x: 10 values are requested in this order PTR0 PTR1 PTR2

@@ -128,16 +155,18 @@ phyc attributes: MR2 MR3

• for STM32MP13x: 6 values are requested in this order

• DX0DLLCR
  

• DX0DQTR
  

• DX0DQSTR
  

• DX1DLLCR
  

• DX1DQTR
  

• DX1DQSTR
  

Example:

/ { soc {

• u-boot,dm-spl;
  

• ddr: ddr@0x5A003000{

• 	u-boot,dm-spl;
  

• 	u-boot,dm-pre-reloc;
  

• compatible = "st,stm32mp1-ddr";
  
  reg = <0x5A003000 0x550
  

diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 49b1262461..a6c19af972 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -230,29 +230,29 @@ static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width)

reg = readl(&ctl->addrmap3); /* addrmap3.addrmap_col_b6 */

• val = (reg & GENMASK(3, 0)) >> 0;

• val = (reg & GENMASK(4, 0)) >> 0; if (val <= 7) bits++; /* addrmap3.addrmap_col_b7 */

• val = (reg & GENMASK(11, 8)) >> 8;

• val = (reg & GENMASK(12, 8)) >> 8; if (val <= 7) bits++; /* addrmap3.addrmap_col_b8 */

• val = (reg & GENMASK(19, 16)) >> 16;

• val = (reg & GENMASK(20, 16)) >> 16; if (val <= 7) bits++; /* addrmap3.addrmap_col_b9 */

• val = (reg & GENMASK(27, 24)) >> 24;

• val = (reg & GENMASK(28, 24)) >> 24; if (val <= 7) bits++;

  reg = readl(&ctl->addrmap4); /* addrmap4.addrmap_col_b10 */

• val = (reg & GENMASK(3, 0)) >> 0;

• val = (reg & GENMASK(4, 0)) >> 0; if (val <= 7) bits++; /* addrmap4.addrmap_col_b11 */

• val = (reg & GENMASK(11, 8)) >> 8;

• val = (reg & GENMASK(12, 8)) >> 8; if (val <= 7) bits++;

@@ -296,21 +296,24 @@ static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) reg = readl(&ctl->addrmap6); /* addrmap6.addrmap_row_b12 */ val = (reg & GENMASK(3, 0)) >> 0;

• if (val <= 7)

• if (val <= 11) bits++; /* addrmap6.addrmap_row_b13 */ val = (reg & GENMASK(11, 8)) >> 8;

• if (val <= 7)

• if (val <= 11) bits++; /* addrmap6.addrmap_row_b14 */ val = (reg & GENMASK(19, 16)) >> 16;

• if (val <= 7)

• if (val <= 11) bits++; /* addrmap6.addrmap_row_b15 */ val = (reg & GENMASK(27, 24)) >> 24;

• if (val <= 7)

• if (val <= 11) bits++;

• if (reg & BIT(31))

• printf("warning: LPDDR3_6GB_12GB is not supported\n");
  

• return bits;

}

@@ -392,12 +395,17 @@ static struct ram_ops stm32mp1_ddr_ops = { .get_info = stm32mp1_ddr_get_info, };

+static const struct stm32mp1_ddr_cfg stm32mp13x_ddr_cfg = {

• .nb_bytes = 2,

+};

static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = { .nb_bytes = 4, };

static const struct udevice_id stm32mp1_ddr_ids[] = { { .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},

• { .compatible = "st,stm32mp13-ddr", .data = (ulong)&stm32mp13x_ddr_cfg}, { }

};

Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com

Thanks Patrice