Hi Stefano,
On 08/11/2012 12:37, Stefano Babic wrote:
On 10/08/2012 20:51, Benoît Thébaudeau wrote:
Since the input frequency of the API is a maximum that should not be exceeded in order for the devices to operate properly, the SPI clock divider should be rounded up, not truncated.
Hi Benoît,
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Wolfgang Denk wd@denx.de Cc: Stefano Babic sbabic@denx.de
.../drivers/spi/mxc_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git u-boot-4d3c95f.orig/drivers/spi/mxc_spi.c u-boot-4d3c95f/drivers/spi/mxc_spi.c index 2e15318..cf1462f 100644 --- u-boot-4d3c95f.orig/drivers/spi/mxc_spi.c +++ u-boot-4d3c95f/drivers/spi/mxc_spi.c @@ -96,7 +96,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
clk_src = mxc_get_clock(MXC_CSPI_CLK);
- div = clk_src / max_hz;
div = DIV_ROUND_UP(clk_src, max_hz); div = get_cspi_div(div);
debug("clk %d Hz, div %d, real clk %d Hz\n",
@@ -147,7 +147,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, * The following computation is taken directly from Freescale's code. */ if (clk_src > max_hz) {
pre_div = clk_src / max_hz;
pre_div = DIV_ROUND_UP(clk_src, max_hz);Agree - do you also get a case where the divider was too low and the SPI does not work or it was only examining the code ?
It was only examining the code. I had many clock issues on i.MX51, so I made a global review of clock usage that led to that. Most i.MX5 clock functions are broken. I have a series fixing these that I will post next week.
Acked-by: Stefano Babic sbabic@denx.de
Best regards, Stefano Babic
Best regards, Benoît