4 Mar
2014
4 Mar
'14
8:14 p.m.
On Tue, Feb 18, 2014 at 07:32:01AM -0500, Tom Rini wrote:
From: Dave Gerlach d-gerlach@ti.com
The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value.
Signed-off-by: Dave Gerlach d-gerlach@ti.com
Applied to u-boot-ti/master, thanks!
--
Tom