From: Tien Fong Chee tien.fong.chee@intel.com
SPL configures DDR by programming peripheral raw binary file and calibrating DDR.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com --- arch/arm/mach-socfpga/spl.c | 43 +++++++++++++++++++++++++++++++++++++++ configs/socfpga_arria10_defconfig | 17 +++++++++++++--- 2 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index aba116d..60159b2 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -15,13 +15,19 @@ #include <asm/arch/system_manager.h> #include <asm/arch/freeze_controller.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/fpga_manager.h> #include <asm/arch/misc.h> #include <asm/arch/scan_manager.h> #include <asm/arch/sdram.h> #include <asm/arch/scu.h> #include <asm/arch/nic301.h> #include <asm/sections.h> +#include <environment.h> #include <fdtdec.h> +#include <fat.h> +#include <fs.h> +#include <linux/ctype.h> +#include <mmc.h> #include <watchdog.h> #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include <asm/arch/pinmux.h> @@ -29,6 +35,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define BSIZE 4096 +#define PERIPH_RBF 0 + #if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; @@ -197,6 +206,12 @@ void board_init_f(ulong dummy) #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) void spl_board_init(void) { + int rval = 0; + int len = 0; + u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN); + struct spl_boot_device bootdev; + fpga_fs_info fpga_fsinfo; + /* configuring the clock based on handoff */ cm_basic_init(gd->fdt_blob); WATCHDOG_RESET(); @@ -214,6 +229,34 @@ void spl_board_init(void)
/* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + + set_default_env(NULL); + + bootdev.boot_device = spl_boot_device(); + + if (BOOT_DEVICE_MMC1 == bootdev.boot_device) { + fpga_fsinfo.interface = "mmc"; + fpga_fsinfo.fstype = FS_TYPE_FAT; + } + + fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob, + &len, + PERIPH_RBF); + + fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd->fdt_blob, + &len); + + if (fpga_fsinfo.dev_part) + env_set("FW_DEV_PART", fpga_fsinfo.dev_part); + + /* Program peripheral RBF */ + rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo); + + if (!rval) { + config_pins(gd->fdt_blob, "shared"); + + ddr_calibration_sequence(); + } }
void board_init_f(ulong dummy) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index f7bcce3..f85064b 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -7,28 +7,39 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" +CONFIG_FIT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FIT=y CONFIG_SPL=y CONFIG_SPL_FPGA_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=32768 CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y +CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_DOS_PARTITION=y -# CONFIG_SPL_DOS_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DOS_PARTITION=y +CONFIG_SPL_FS_GENERIC=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y +CONFIG_MMC_DW=y CONFIG_SYS_NS16550=y CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_SPL_MMC_SUPPORT=y