From: T Karthik Reddy t.karthik.reddy@amd.com
The spi-nor framework will set up the flash parameters by reading the flash id table flags, which include cmd opcodes, address width, dummy bytes, and bus width. In case, flash supports octal DTR mode and the controller does not support the DTR. There is no process to switch back to SDR mode. To avoid this issue, create a Kconfig option SPI_FLASH_DTR_ENABLE to explicitly specify to enable/disable flash DTR support. This config is disabled by default. Do not initialize the mt35xu512aba post sfdp fixups unless SPI_FLASH_DTR_ENABLE is enabled to avoid configuring DTR.
Signed-off-by: T Karthik Reddy t.karthik.reddy@amd.com Co-developed-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/Kconfig | 7 +++++++ drivers/mtd/spi/spi-nor-core.c | 12 +++++++++--- 2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 732b076045..e0898074a2 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -202,6 +202,13 @@ config SPI_FLASH_MT35XU because the fixup hooks for this flash add extra size overhead. Boards that don't use the flash can disable this to save space.
+config SPI_FLASH_DTR_ENABLE + bool "Enable Flash DTR support" + help + Select this config to enable DTR mode by spi-nor framework. + This config provides an option to explicitly enable/disable the DTR + support even though the flash id flags specify flash supports DTR mode. + config SPI_FLASH_SST bool "SST SPI flash support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5c3ffc80eb..473d9f41f3 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2962,7 +2962,8 @@ static int spi_nor_init_params(struct spi_nor *nor, SNOR_PROTO_1_1_8); }
- if (info->flags & SPI_NOR_OCTAL_DTR_READ) { + if (CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE) && + info->flags & SPI_NOR_OCTAL_DTR_READ) { params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], 0, 20, SPINOR_OP_READ_FAST, @@ -2978,8 +2979,10 @@ static int spi_nor_init_params(struct spi_nor *nor, * Since xSPI Page Program opcode is backward compatible with * Legacy SPI, use Legacy SPI opcode there as well. */ - spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], - SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); + if (CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE)) { + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], + SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); + }
if (info->flags & SPI_NOR_QUAD_READ) { params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; @@ -4011,6 +4014,9 @@ static void mt35xu512aba_default_init(struct spi_nor *nor) static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { + if (!CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE)) + return; + /* Set the Fast Read settings. */ params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],