Hi,
Maybe you have any comments or remarks about this patch? And if you don't could you please apply it.
Thanks!
On Tue, 2017-09-26 at 16:10 +0300, Eugeniy Paltsev wrote:
Add option to set spi controller clock frequency via device tree using standard clock bindings. Old way of setting spi controller clock frequency (via implementation of 'cm_get_spi_controller_clk_hz' function in platform specific code) remains supported.
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com
Resending due to previously sent one was discarded by mailing list.
drivers/spi/designware_spi.c | 68 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5aa507b..c70697e 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> @@ -94,6 +95,7 @@ struct dw_spi_priv { void __iomem *regs; unsigned int freq; /* Default frequency */ unsigned int mode;
- unsigned long bus_clk_rate;
int bits_per_word; u8 cs; /* chip select pin */ @@ -176,14 +178,78 @@ static void spi_hw_init(struct dw_spi_priv *priv) debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); } +/*
- cm_get_spi_controller_clk_hz function is old way to set spi controller
- frequency. If it isn't implemented and spi controller frequency isn't set via
- device tree we will get into next default function.
- */
+__weak unsigned int cm_get_spi_controller_clk_hz(void) +{
- error("SPI clock is defined neither via device tree nor via cm_get_spi_controller_clk_hz!");
- return 0;
+}
+static int dw_spi_of_get_clk(struct udevice *bus) +{ +#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
- struct dw_spi_priv *priv = dev_get_priv(bus);
- unsigned long clk_rate;
- struct clk clk;
- int ret;
- ret = clk_get_by_index(bus, 0, &clk);
- if (ret)
return -EINVAL;- ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS)
return ret;- clk_rate = clk_get_rate(&clk);
- if (!clk_rate)
return -EINVAL;- priv->bus_clk_rate = clk_rate;
- clk_free(&clk);
- return 0;
+#endif
- return -ENOSYS;
+}
+static int dw_spi_get_clk(struct udevice *bus) +{
- struct dw_spi_priv *priv = dev_get_priv(bus);
- /* Firstly try to get clock frequency from device tree */
- if (!dw_spi_of_get_clk(bus))
return 0;- /* In case of failure rollback to cm_get_spi_controller_clk_hz */
- priv->bus_clk_rate = cm_get_spi_controller_clk_hz();
- if (!priv->bus_clk_rate)
return -EINVAL;- return 0;
+}
static int dw_spi_probe(struct udevice *bus) { struct dw_spi_platdata *plat = dev_get_platdata(bus); struct dw_spi_priv *priv = dev_get_priv(bus);
- int ret;
priv->regs = plat->regs; priv->freq = plat->frequency;
- ret = dw_spi_get_clk(bus);
- if (ret)
return ret;/* Currently only bits_per_word == 8 supported */ priv->bits_per_word = 8; @@ -369,7 +435,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed) spi_enable_chip(priv, 0); /* clk_div doesn't support odd number */
- clk_div = cm_get_spi_controller_clk_hz() / speed;
- clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe; dw_writel(priv, DW_SPI_BAUDR, clk_div);