On Fri, Jun 10, 2016 at 8:35 AM, Simon Glass sjg@chromium.org wrote:
On 8 June 2016 at 06:07, Bin Meng bmeng.cn@gmail.com wrote:
At present all BayTrail boards configure fsp,emmc-boot-mode to 2, which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1 only shows up on some early stepping silicon of BayTrail SoC. Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP provides a config option fsp,emmc-boot-mode which tells FSP which eMMC controller it initializes. Instead of hardcoded to 2, now we change it to 1 which means "auto".
With this change, MinnowMax board (with a D0 stepping BayTrail SoC) can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot 'pci' command.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/dts/bayleybay.dts | 2 +- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- arch/x86/dts/minnowmax.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!