ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled.
Signed-off-by: Aneesh Bansal aneesh.bansal@freescale.com --- arch/powerpc/cpu/mpc85xx/start.S | 58 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5440bf5..2b2c4dd 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -116,6 +116,64 @@ _start_e500: mtspr SPRN_HDBCR0, r3 #endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \ + !defined(CONFIG_E500MC) + /* ISBC creates a LAW 0 entry for non PBL platforms, + * which is not disabled before transferring the control to uboot. + * Disable the LAW 0 entry here. + */ + + /* create a temp TLB mapping for CCSRBAR */ + lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l + + lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR_DEFAULT, + (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR_DEFAULT, + (MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, + (MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, + (MAS3_SW|MAS3_SR))@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe + + /* Clear the LAW 0 entry */ + lis r3, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r3, r3, CONFIG_SYS_CCSRBAR_DEFAULT@l + li r4, 0x0 + + stw r4, 0xc10(r3) /* LAWAR0 */ + sync + + /* clear the TLB mapping for CCSRBAR */ + lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l + + lis r7,FSL_BOOKE_MAS1(0, 0, 0, 0, 0)@h + ori r7,r7,FSL_BOOKE_MAS1(0, 0, 0, 0, 0)@l + + li r8, 0x0 + li r9, 0x0 + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + isync + msync + tlbwe +#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ !defined(CONFIG_E6500)