Index: cpu/mpc85xx/tsec.c
===================================================================
RCS file: /cm/vault/u-boot/u-boot/cpu/mpc85xx/tsec.c,v
retrieving revision 1.1.1.2.2.11
diff -a -u -r1.1.1.2.2.11 tsec.c
--- cpu/mpc85xx/tsec.c	12 May 2005 19:57:13 -0000	1.1.1.2.2.11
+++ cpu/mpc85xx/tsec.c	19 May 2005 20:20:45 -0000
@@ -35,7 +35,7 @@
 
 struct tsec_info_struct {
 	unsigned int phyaddr;
-	unsigned int gigabit;
+	u32 flags;
 	unsigned int phyregidx;
 };
 
@@ -48,8 +48,9 @@
  *  phyaddr - The address of the PHY which is attached to
  *	the given device.
  *
- *  gigabit - This variable indicates whether the device
- *	supports gigabit speed ethernet
+ *  flags - This variable indicates whether the device
+ *	supports gigabit speed ethernet, and whether it should be
+ *	in reduced mode.
  *
  *  phyregidx - This variable specifies which ethernet device
  *	controls the MII Management registers which are connected
@@ -70,12 +71,12 @@
  */
 static struct tsec_info_struct tsec_info[] = {
 #ifdef CONFIG_MPC85XX_TSEC1
-	{TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX},
+	{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
 #else
 	{ 0, 0, 0},
 #endif
 #ifdef CONFIG_MPC85XX_TSEC2
-	{TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX},
+	{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
 #else
 	{ 0, 0, 0},
 #endif
@@ -83,12 +84,12 @@
 	{FEC_PHY_ADDR, 0, FEC_PHYIDX},
 #else
 #    ifdef CONFIG_MPC85XX_TSEC3
-	{TSEC3_PHY_ADDR, 1, TSEC3_PHYIDX},
+	{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
 #    else
 	{ 0, 0, 0},
 #    endif
 #    ifdef CONFIG_MPC85XX_TSEC4
-	{TSEC4_PHY_ADDR, 1, TSEC4_PHYIDX},
+	{TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
 #    else
 	{ 0, 0, 0},
 #    endif
@@ -124,7 +125,7 @@
 /* Initialize device structure. Returns success if PHY
  * initialization succeeded (i.e. if it recognizes the PHY)
  */
-int tsec_initialize(bd_t *bis, int index)
+int tsec_initialize(bd_t *bis, int index, char *devname)
 {
 	struct eth_device* dev;
 	int i;
@@ -148,9 +149,9 @@
 			tsec_info[index].phyregidx*TSEC_SIZE);
 
 	priv->phyaddr = tsec_info[index].phyaddr;
-	priv->gigabit = tsec_info[index].gigabit;
+	priv->flags = tsec_info[index].flags;
 
-	sprintf(dev->name, "ENET%d", index);
+	sprintf(dev->name, devname);
 	dev->iobase = 0;
 	dev->priv   = priv;
 	dev->init   = tsec_init;
@@ -327,7 +328,7 @@
 /* For 10/100, the value is slightly different */
 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
 {
-	if(priv->gigabit)
+	if(priv->flags & TSEC_GIGABIT)
 		return MIIM_CONTROL_INIT;
 	else
 		return MIIM_CR_INIT;
@@ -447,6 +448,13 @@
 	return MIIM_CIS8204_SLEDCON_INIT;
 }
 
+uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
+{
+	if (priv->flags & TSEC_REDUCED)
+		return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
+	else
+		return MIIM_CIS8204_EPHYCON_INIT;
+}
 
 /* Initialized required registers to appropriate values, zeroing
  * those we don't care about (unless zero is bad, in which case,
@@ -516,6 +524,15 @@
 			case 10:
 				regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
 					| MACCFG2_MII);
+
+				/* If We're in reduced mode, we
+				 * need to say whether we're 10
+				 * or 100 MB. */
+				if ((priv->speed == 100) 
+						&& (priv->flags & TSEC_REDUCED))
+					regs->ecntrl |= ECNTRL_R100;
+				else
+					regs->ecntrl &= ~(ECNTRL_R100);
 				break;
 			default:
 				printf("%s: Speed was bad\n", dev->name);
@@ -740,7 +757,7 @@
 		/* Configure some basic stuff */
 		{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 		{MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
-		{MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL},
+		{MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
 		{miim_end,}
 	},
 	(struct phy_cmd[]) { /* startup */
Index: cpu/mpc85xx/tsec.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/cpu/mpc85xx/tsec.h,v
retrieving revision 1.1.1.1.4.5
diff -a -u -r1.1.1.1.4.5 tsec.h
--- cpu/mpc85xx/tsec.h	5 May 2005 21:33:52 -0000	1.1.1.1.4.5
+++ cpu/mpc85xx/tsec.h	19 May 2005 20:20:45 -0000
@@ -51,6 +51,7 @@
 
 #define ECNTRL_INIT_SETTINGS	0x00001000
 #define ECNTRL_TBI_MODE         0x00000020
+#define ECNTRL_R100		0x00000008
 
 #define miim_end -2
 #define miim_read -1
@@ -107,6 +108,7 @@
 /* Cicada 8204 Extended PHY Control Register 1 */
 #define MIIM_CIS8204_EPHY_CON		0x17
 #define MIIM_CIS8204_EPHYCON_INIT	0x0006
+#define MIIM_CIS8204_EPHYCON_RGMII	0x1000
 
 /* Cicada 8204 Serial LED Control Register */
 #define MIIM_CIS8204_SLED_CON		0x1b
@@ -424,12 +426,18 @@
 	uint	resc00[256];
 } tsec_t;
 
+#define TSEC_GIGABIT (1)
+
+/* This flag currently only has
+ * meaning if we're using the eTSEC */
+#define TSEC_REDUCED (1 << 1)
+
 struct tsec_private {
 	volatile tsec_t *regs;
 	volatile tsec_t *phyregs;
 	struct phy_info *phyinfo;
 	uint phyaddr;
-	uint gigabit;
+	u32 flags;
 	uint link;
 	uint duplexity;
 	uint speed;
Index: include/configs/MPC8540ADS.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/MPC8540ADS.h,v
retrieving revision 1.1.1.1.4.20
diff -a -u -r1.1.1.1.4.20 MPC8540ADS.h
--- include/configs/MPC8540ADS.h	5 May 2005 15:06:35 -0000	1.1.1.1.4.20
+++ include/configs/MPC8540ADS.h	19 May 2005 20:20:46 -0000
@@ -344,7 +344,9 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
@@ -353,11 +355,13 @@
 
 #if CONFIG_HAS_FEC
 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
 #endif
 
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
Index: include/configs/MPC8541CDS.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/MPC8541CDS.h,v
retrieving revision 1.1.2.8
diff -a -u -r1.1.2.8 MPC8541CDS.h
--- include/configs/MPC8541CDS.h	5 May 2005 15:06:35 -0000	1.1.2.8
+++ include/configs/MPC8541CDS.h	19 May 2005 20:20:46 -0000
@@ -363,7 +363,9 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -371,7 +373,9 @@
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define FEC_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
Index: include/configs/MPC8548CDS.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/Attic/MPC8548CDS.h,v
retrieving revision 1.1.4.3
diff -a -u -r1.1.4.3 MPC8548CDS.h
--- include/configs/MPC8548CDS.h	12 May 2005 19:57:14 -0000	1.1.4.3
+++ include/configs/MPC8548CDS.h	19 May 2005 20:20:46 -0000
@@ -369,9 +369,13 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
 #define CONFIG_MPC85XX_TSEC3	1
+#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
 #define CONFIG_MPC85XX_TSEC4	1
+#define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		0
@@ -386,7 +390,8 @@
 #define TSEC4_PHYIDX		0
 #define FEC_PHYIDX		0
 
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
Index: include/configs/MPC8555CDS.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/MPC8555CDS.h,v
retrieving revision 1.1.4.29
diff -a -u -r1.1.4.29 MPC8555CDS.h
--- include/configs/MPC8555CDS.h	5 May 2005 15:06:35 -0000	1.1.4.29
+++ include/configs/MPC8555CDS.h	19 May 2005 20:20:46 -0000
@@ -363,7 +363,9 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
@@ -371,7 +373,9 @@
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 #define FEC_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #endif	/* CONFIG_TSEC_ENET */
 
Index: include/configs/MPC8560ADS.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/MPC8560ADS.h,v
retrieving revision 1.1.1.1.4.20
diff -a -u -r1.1.1.1.4.20 MPC8560ADS.h
--- include/configs/MPC8560ADS.h	5 May 2005 15:06:35 -0000	1.1.1.1.4.20
+++ include/configs/MPC8560ADS.h	19 May 2005 20:20:46 -0000
@@ -339,13 +339,17 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
Index: include/configs/PM854.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/PM854.h,v
retrieving revision 1.1.1.1.2.2
diff -a -u -r1.1.1.1.2.2 PM854.h
--- include/configs/PM854.h	6 May 2005 17:00:25 -0000	1.1.1.1.2.2
+++ include/configs/PM854.h	19 May 2005 20:20:46 -0000
@@ -252,17 +252,21 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		3
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 
 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		1
 #define FEC_PHYIDX		0
 
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #define	CONFIG_HAS_ETH1		1
 #define	CONFIG_HAS_ETH2		1
Index: include/configs/SBC8540.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/SBC8540.h,v
retrieving revision 1.1.2.3
diff -a -u -r1.1.2.3 SBC8540.h
--- include/configs/SBC8540.h	1 Feb 2005 19:17:15 -0000	1.1.2.3
+++ include/configs/SBC8540.h	19 May 2005 20:20:46 -0000
@@ -227,10 +227,14 @@
 
 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
 
-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S		/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
 
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
Index: include/configs/SBC8560.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/SBC8560.h,v
retrieving revision 1.1.2.3
diff -a -u -r1.1.2.3 SBC8560.h
--- include/configs/SBC8560.h	1 Feb 2005 19:17:15 -0000	1.1.2.3
+++ include/configs/SBC8560.h	19 May 2005 20:20:46 -0000
@@ -215,10 +215,14 @@
 
 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
 
-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S		/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
 
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
Index: include/configs/TQM8540.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/TQM8540.h,v
retrieving revision 1.1.1.1.2.1
diff -a -u -r1.1.1.1.2.1 TQM8540.h
--- include/configs/TQM8540.h	5 May 2005 21:34:09 -0000	1.1.1.1.2.1
+++ include/configs/TQM8540.h	19 May 2005 20:20:46 -0000
@@ -281,16 +281,19 @@
 #define CONFIG_MII		1	/* MII PHY management */
 #undef CONFIG_MPC85XX_TSEC1
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
 
 #define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
 #define FEC_PHY_ADDR		0
 #define FEC_PHYIDX		0
 
-#define CONFIG_ETHPRIME		"ENET1"
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC1"
 
 #endif	/* CONFIG_TSEC_ENET */
 
Index: include/configs/TQM8560.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/TQM8560.h,v
retrieving revision 1.1.1.1.2.1
diff -a -u -r1.1.1.1.2.1 TQM8560.h
--- include/configs/TQM8560.h	5 May 2005 21:34:09 -0000	1.1.1.1.2.1
+++ include/configs/TQM8560.h	19 May 2005 20:20:46 -0000
@@ -276,6 +276,7 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #define TSEC2_PHY_ADDR		1
 #define TSEC2_PHYIDX		0
 
@@ -288,7 +289,7 @@
 #define CFG_CPMFCR_RAMTYPE    0
 #define CFG_FCC_PSMR          (FCC_PSMR_FDE | FCC_PSMR_LPB)
 
-#define CONFIG_ETHPRIME		"ENET1"
+#define CONFIG_ETHPRIME		"TSEC1"
 
 /*
  * Environment
Index: include/configs/sbc8560.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/sbc8560.h,v
retrieving revision 1.1.2.3
diff -a -u -r1.1.2.3 sbc8560.h
--- include/configs/sbc8560.h	1 Feb 2005 19:17:16 -0000	1.1.2.3
+++ include/configs/sbc8560.h	19 May 2005 20:20:46 -0000
@@ -210,10 +210,14 @@
 
 #if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
 
-  #define CONFIG_NET_MULTI	1
-  #define CONFIG_PHY_BCM5421S	1	/* GigaBit Ether PHY	     */
-  #define CONFIG_MII		1	/* MII PHY management		*/
-  #define CONFIG_PHY_ADDR	25	/* PHY address			*/
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
Index: include/configs/stxgp3.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/configs/stxgp3.h,v
retrieving revision 1.1.2.7
diff -a -u -r1.1.2.7 stxgp3.h
--- include/configs/stxgp3.h	1 Feb 2005 19:17:16 -0000	1.1.2.7
+++ include/configs/stxgp3.h	19 May 2005 20:20:47 -0000
@@ -227,14 +227,16 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 
 #define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
 #define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		4
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
-#define CONFIG_ETHPRIME		"MOTO ENET0"
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
Index: net/eth.c
===================================================================
RCS file: /cm/vault/u-boot/u-boot/net/eth.c,v
retrieving revision 1.1.1.2.2.5
diff -a -u -r1.1.1.2.2.5 eth.c
--- net/eth.c	12 May 2005 19:57:14 -0000	1.1.1.2.2.5
+++ net/eth.c	19 May 2005 20:20:47 -0000
@@ -52,7 +52,7 @@
 extern int rtl8169_initialize(bd_t*);
 extern int scc_initialize(bd_t*);
 extern int skge_initialize(bd_t*);
-extern int tsec_initialize(bd_t*, int);
+extern int tsec_initialize(bd_t*, int, char *);
 
 static struct eth_device *eth_devices, *eth_current;
 
@@ -155,19 +155,19 @@
 	skge_initialize(bis);
 #endif
 #if defined(CONFIG_MPC85XX_TSEC1)
-	tsec_initialize(bis, 0);
+	tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME);
 #endif
 #if defined(CONFIG_MPC85XX_TSEC2)
-	tsec_initialize(bis, 1);
+	tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME);
 #endif
 #if defined(CONFIG_MPC85XX_FEC)
-	tsec_initialize(bis, 2);
+	tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME);
 #else
 #    if defined(CONFIG_MPC85XX_TSEC3)
-	tsec_initialize(bis, 2);
+	tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME);
 #    endif
 #    if defined(CONFIG_MPC85XX_TSEC4)
-	tsec_initialize(bis, 3);
+	tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME);
 #    endif
 #endif
 #if defined(CONFIG_AU1X00)
