This should make it clear that this symbol is meant to be defined by board headers.
Signed-off-by: Phil Sutter phil@nwl.cc --- drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 +- drivers/ddr/marvell/axp/ddr3_axp_mc_static.h | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index 25c34fb..8549fe8 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -51,7 +51,7 @@ #define DRAM_ECC 0 #endif
-#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT #define BUS_WIDTH 32 #else #define BUS_WIDTH 64 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h index 2c0e9075..71794ad 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h @@ -8,9 +8,9 @@ #define __AXP_MC_STATIC_H
MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -66,9 +66,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { };
MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -124,9 +124,9 @@ MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { };
MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /* MV_DDR_64BIT */ +#else /* CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B840}, /*Dunit Control Low Register */ @@ -176,9 +176,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { };
MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B040}, /*Dunit Control Low Register */ @@ -233,9 +233,9 @@ MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { };
MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */ #endif