On 04/17/2012 03:18 PM, Simon Glass wrote:
+Jim, who wrote the driver originally
Hi Scott,
On Tue, Apr 17, 2012 at 12:06 PM, Scott Wood scottwood@freescale.com wrote:
- nvidia,page-data-bytes : Number of bytes in the data area
- nvidia,page-spare-bytes : Number of bytes in spare area
spare area = skipped-spare-bytes + data-ecc-bytes + tag-bytes+ tag-ecc-bytesDo you really need this stuff to be in the device tree? You should be able to determine this information from the ID table.
I suspect so - the driver originally had a lot of CONFIGs for this. Maybe someone who wants to take it further could do this as part of supporting ONFI?
I will see if Jim Lin can take another look.
You don't need ONFI to get the page/spare size out of the ID table.
The generic NAND code should already be doing this for you (fills in mtd->writesize and mtd->oobsize). If you need it during setup, we now have CONFIG_SYS_NAND_SELF_INIT that allows splitting up nand_scan_ident() from nand_scan_tail().
+Nvidia NAND Controller +----------------------
+The device node for a NAND flash controller is as follows:
+Optional properties:
+nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
phandle, parameter, flagsDoesn't the number of cells depend on the GPIO controller binding?
Yes, but this is the binding Tegra uses.
Still, it doesn't belong in the NAND binding. Maybe a future chip wants to use this NAND binding but a different GPIO binding. If nothing else, people tend to copy-and-paste such descriptions. We've still got people adding bindings for Freescale devices saying interrupts are encoded as a pair of cells, even though the interrupt controller now uses four cells per interrupt.
-Scott