Dear Gachet Daniel,
This patch v2 correct corrupted data while reading NAND flash modules on the KARO TX25 module.
The current version of the mxc_nand driver uses the symmetric mode to access the NAND flash, but the devices populated on the KARO TX25 only support an asymmetric mode (i.MX25: bit 8 within NAND_FLASH_CONFIG1 register cleared).
To solve the problem in a generic way, the proposition is to define a specific value for that bit, CONFIG_NAND_MXC_NFC_ONE_CYCLE. This value could be defined in the specific board configuration file (./include/configs/...). Short description:
CONFIG_NAND_MXC_NFC_ONE_CYCLE enables to specify how to access NAND flash on the i.MX25 CPU. If CONFIG_NAND_MXC_NFC_ONE_CYCLE is defined, a one-clock cycle will be used to access the NAND flash (symmetric mode); otherwise a two-clock cycle will be used (asymmetric mode).
Signed-off-by: Daniel Gachet daniel.gachet@hefr.ch Cc: stefano babic sbabic@denx.de
diff -upr drivers/mtd/nand/mxc_nand.c drivers/mtd/nand/mxc_nand.c --- drivers/mtd/nand/mxc_nand.c 2011-12-23 20:25:35.000000000 +0100 +++ drivers/mtd/nand/mxc_nand.c 2012-04-02 22:30:13.000000000 +0200 @@ -1290,7 +1290,9 @@ static void mxc_setup_config1(void) uint16_t tmp;
tmp = readw(&host->regs->nfc_config1); +#ifdef CONFIG_NAND_MXC_NFC_ONE_CYCLE tmp |= NFC_ONE_CYCLE; +#endif tmp |= NFC_4_8N_ECC; writew(tmp, &host->regs->nfc_config1); if (host->pagesize_2k)
Won't this break other MX25 boards? Stefano?
Best regards, Marek Vasut