Am 04.07.2019 um 10:56 schrieb Ley Foon Tan:
Add SPL support for Agilex SoC.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
From all I can tell right now, seems good to me:
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v2:
- Change clock driver probing to DM.
- Remove unused OSC1TIMER0 reset
- Remove debug_uart_init(). UART depends on clock driver setup, no point to call debug_uart_init() after spl_early_init() and clock driver initialization.
arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/spl_agilex.c | 100 +++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm/mach-socfpga/spl_agilex.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 51355ad070..476dcaefff 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -61,6 +61,7 @@ obj-y += spl_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += ccu_agilex.o +obj-y += spl_agilex.o endif endif
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c new file mode 100644 index 0000000000..0cc0a7f798 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <common.h> +#include <image.h> +#include <spl.h> +#include <asm/arch/ccu_agilex.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <watchdog.h> +#include <dm/uclass.h>
+DECLARE_GLOBAL_DATA_PTR;
+static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+u32 spl_boot_device(void) +{
- return BOOT_DEVICE_MMC1;
+}
+#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- return MMCSD_MODE_FS;
+#else
- return MMCSD_MODE_RAW;
+#endif +} +#endif
+void board_init_f(ulong dummy) +{
- int ret;
- struct udevice *dev;
+#ifdef CONFIG_HW_WATCHDOG
- /* Ensure watchdog is paused when debugging is happening */
- writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
- /* Enable watchdog before initializing the HW */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
- hw_watchdog_init();
+#endif
- /* ensure all processors are not released prior Linux boot */
- writeq(0, CPU_RELEASE_ADDR);
- timer_init();
- sysmgr_pinmux_init();
- ret = spl_early_init();
- if (ret) {
debug("spl_early_init() failed: %d\n", ret);hang();- }
- ret = uclass_get_device(UCLASS_CLK, 0, &dev);
- if (ret) {
debug("Clock init failed: %d\n", ret);hang();- }
- preloader_console_init();
- cm_print_clock_quick_summary();
- /* enable non-secure interface to DMA330 DMA and peripherals */
- writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
- writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
- firewall_setup();
- ccu_init();
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
debug("DRAM init failed: %d\n", ret);hang();- }
+#endif
- mbox_init();
+#ifdef CONFIG_CADENCE_QSPI
- mbox_qspi_open();
+#endif +}