Since flash_info hadle all read modes through e_rd_cmd there is no explicit flags for these, hence removed the same.
Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Michal Simek michal.simek@xilinx.com Cc: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Jagan Teki jteki@openedev.com --- drivers/mtd/spi/spi_flash.c | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index b22b79a..8d2871f 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -52,8 +52,6 @@ struct flash_info { #define SST_WRITE 0x04 /* use SST byte programming */ #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ -#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ -#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ #define USE_FSR 0x80 /* use flag status register */ }; #define JEDEC_MFR(info) ((info)->id[0]) @@ -999,20 +997,20 @@ static const struct flash_info spi_flash_ids[] = { { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, RD_FULL, WR_QPP) }, { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, RD_FULL, WR_QPP) }, { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, RD_FULL, WR_QPP) }, - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, RD_FULL, WR_QPP | SPI_NOR_QUAD_READ) }, - { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, RD_FULL, WR_QPP | SPI_NOR_QUAD_READ) }, + { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, RD_FULL, WR_QPP) }, + { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, RD_FULL, WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ /* Micron */ - { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, RD_FULL, WR_QPP | SPI_NOR_QUAD_READ) }, - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, RD_FULL, WR_QPP | SPI_NOR_QUAD_READ) }, - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, RD_FULL, WR_QPP | SPI_NOR_QUAD_READ) }, - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, RD_FULL, WR_QPP | SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, RD_FULL, WR_QPP | SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, RD_FULL, WR_QPP | SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, RD_FULL, WR_QPP) }, + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K) }, + { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K) }, + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, RD_FULL, WR_QPP) }, + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, RD_FULL, WR_QPP) }, + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K) }, + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, RD_FULL, WR_QPP | SECT_4K | USE_FSR) }, + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, RD_FULL, WR_QPP | SECT_4K | USE_FSR) }, + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, RD_FULL, WR_QPP | SECT_4K | USE_FSR) }, #endif /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, RD_NORM, SECT_4K_PMC) }, @@ -1023,19 +1021,19 @@ static const struct flash_info spi_flash_ids[] = { /* Spansion -- single (large) sector size only, at least * for the chips listed here (without boot sectors). */ - { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, 0) }, + { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, 0) }, { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP) }, - { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, 0) }, + { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, 0) }, { "s25fl512s1", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP) }, { "s25fl512s2", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP) }, { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP) }, { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP) }, { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP) }, - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K | SPI_NOR_QUAD_READ) }, - { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K) }, + { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP) }, + { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP) }, { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, RD_NORM, 0) }, { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, RD_NORM, 0) }, { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, RD_NORM, 0) },