Enable OP-TEE resources and SMCI over OP-TEE on STM32MP15xx-EV1/DK2 boards.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- arch/arm/dts/stm32mp15-u-boot.dtsi | 81 +++++------ arch/arm/dts/stm32mp151.dtsi | 145 ++++++++++++-------- arch/arm/dts/stm32mp153.dtsi | 6 +- arch/arm/dts/stm32mp157.dtsi | 2 +- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 114 +-------------- arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 40 ++++++ arch/arm/dts/stm32mp157c-dk2.dts | 9 ++ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 99 +------------ arch/arm/dts/stm32mp157c-ed1.dts | 5 + arch/arm/dts/stm32mp157c-odyssey.dts | 14 ++ arch/arm/dts/stm32mp15xc.dtsi | 4 +- include/dt-bindings/clock/stm32mp1-clks.h | 27 ++++ include/dt-bindings/reset/stm32mp1-resets.h | 14 ++ 13 files changed, 248 insertions(+), 312 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 43a7909978..6fd204c635 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -21,23 +21,11 @@ pinctrl1 = &pinctrl_z; };
- clocks { - u-boot,dm-pre-reloc; - }; - /* need PSCI for sysreset during board_f */ psci { u-boot,dm-pre-proper; };
- reboot { - u-boot,dm-pre-reloc; - compatible = "syscon-reboot"; - regmap = <&rcc>; - offset = <0x404>; - mask = <0x1>; - }; - soc { u-boot,dm-pre-reloc;
@@ -72,36 +60,6 @@ u-boot,dm-pre-reloc; };
-&clk_csi { - u-boot,dm-pre-reloc; -}; - -&clk_hsi { - u-boot,dm-pre-reloc; -}; - -&clk_hse { - u-boot,dm-pre-reloc; -}; - -&clk_lsi { - u-boot,dm-pre-reloc; -}; - -&clk_lse { - u-boot,dm-pre-reloc; -}; - -&cpu0_opp_table { - u-boot,dm-spl; - opp-650000000 { - u-boot,dm-spl; - }; - opp-800000000 { - u-boot,dm-spl; - }; -}; - &gpioa { u-boot,dm-pre-reloc; }; @@ -161,8 +119,8 @@
/* temp = waiting kernel update */ &m4_rproc { - resets = <&rcc MCU_R>, - <&rcc MCU_HOLD_BOOT_R>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; reset-names = "mcu_rst", "hold_boot"; };
@@ -174,6 +132,7 @@ u-boot,dm-pre-reloc; };
+// TODO: remove once PWR under SCMI &pwr_regulators { u-boot,dm-pre-reloc; }; @@ -184,6 +143,38 @@ #size-cells = <0>; };
+&scmi0 { + u-boot,dm-pre-reloc; +}; + +&scmi0_clk { + u-boot,dm-pre-reloc; +}; + +&scmi0_reset { + u-boot,dm-pre-reloc; +}; + +&scmi0_shm { + u-boot,dm-pre-reloc; +}; + +&scmi1 { + u-boot,dm-pre-reloc; +}; + +&scmi1_clk { + u-boot,dm-pre-reloc; +}; + +&scmi1_shm { + u-boot,dm-pre-reloc; +}; + +&scmi_sram { + u-boot,dm-pre-reloc; +}; + &sdmmc1 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; }; @@ -197,7 +188,7 @@ };
&usart1 { - resets = <&rcc USART1_R>; + resets = <&scmi0_reset RST_SCMI0_USART1>; };
&usart2 { diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 8e0a0bc1dd..db48077375 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -48,6 +48,69 @@ interrupt-parent = <&intc>; };
+ scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi0_shm: scmi_shm@0 { + reg = <0 0x80>; + }; + + scmi1_shm: scmi_shm@200 { + reg = <0x200 0x80>; + }; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + + scmi0: scmi0 { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + /* Supply properties for arm,scmi-smc compatible */ + arm,smc-id = <0x82002000>; + shmem = <&scmi0_shm>; + /* Enable only if stm32mp15x RCC[TZEN]=1 */ + status = "disabled"; + + scmi0_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi0_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi1: scmi1 { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <1>; + /* Supply properties for arm,scmi-smc compatible */ + arm,smc-id = <0x82002001>; + shmem = <&scmi1_shm>; + /* Enable only if stm32mp15x RCC[MCKPROT]=1 */ + status = "disabled"; + + scmi1_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -70,38 +133,6 @@ interrupt-parent = <&intc>; };
- clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - }; - }; - thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; @@ -571,7 +602,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; @@ -1143,16 +1174,19 @@ };
rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; + compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, - <&clk_lse>, <&clk_lsi>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, + <&scmi0_clk CK_SCMI0_HSI>, + <&scmi0_clk CK_SCMI0_CSI>, + <&scmi0_clk CK_SCMI0_LSE>, + <&scmi0_clk CK_SCMI0_LSI>; };
+ // TODO: remove once under SCMI pwr_regulators: pwr@50001000 { compatible = "st,stm32mp1,pwr-reg"; reg = <0x50001000 0x10>; @@ -1333,8 +1367,8 @@ compatible = "st,stm32f756-hash"; reg = <0x54002000 0x400>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; + clocks = <&scmi0_clk CK_SCMI0_HASH1>; + resets = <&scmi0_reset RST_SCMI0_HASH1>; dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; @@ -1344,8 +1378,8 @@ rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; + clocks = <&scmi0_clk CK_SCMI0_RNG1>; + resets = <&scmi0_reset RST_SCMI0_RNG1>; status = "disabled"; };
@@ -1354,7 +1388,7 @@ reg = <0x58000000 0x1000>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; + resets = <&scmi0_reset RST_SCMI0_MDMA>; #dma-cells = <5>; dma-channels = <32>; dma-requests = <48>; @@ -1517,7 +1551,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; @@ -1549,7 +1583,7 @@ compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; + clocks = <&scmi0_clk CK_SCMI0_USART1>; wakeup-source; status = "disabled"; }; @@ -1560,8 +1594,8 @@ compatible = "st,stm32h7-spi"; reg = <0x5c001000 0x400>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; + clocks = <&scmi0_clk CK_SCMI0_SPI6>; + resets = <&scmi0_reset RST_SCMI0_SPI6>; dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, <&mdma1 35 0x0 0x40002 0x0 0x0>; dma-names = "rx", "tx"; @@ -1574,8 +1608,8 @@ interrupt-names = "event", "error"; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; + clocks = <&scmi0_clk CK_SCMI0_I2C4>; + resets = <&scmi0_reset RST_SCMI0_I2C4>; #address-cells = <1>; #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x8>; @@ -1587,7 +1621,8 @@ rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; + clocks = <&scmi0_clk CK_SCMI0_RTCAPB>, + <&scmi0_clk CK_SCMI0_RTC>; clock-names = "pclk", "rtc_ck"; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1615,8 +1650,8 @@ interrupt-names = "event", "error"; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; + clocks = <&scmi0_clk CK_SCMI0_I2C6>; + resets = <&scmi0_reset RST_SCMI0_I2C6>; #address-cells = <1>; #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x20>; @@ -1782,7 +1817,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; - clocks = <&rcc GPIOZ>; + clocks = <&scmi0_clk CK_SCMI0_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; @@ -1804,9 +1839,9 @@ reg = <0x10000000 0x40000>, <0x30000000 0x40000>, <0x38000000 0x10000>; - resets = <&rcc MCU_R>; - st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi index 1c1889b194..e9ba6a9f30 100644 --- a/arch/arm/dts/stm32mp153.dtsi +++ b/arch/arm/dts/stm32mp153.dtsi @@ -13,6 +13,8 @@ clock-frequency = <650000000>; device_type = "cpu"; reg = <1>; + clocks = <&scmi0_clk CK_SCMI0_MPU>; + clock-names = "cpu"; }; };
@@ -30,7 +32,7 @@ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -43,7 +45,7 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi index 54e73ccea4..7b06c08e3a 100644 --- a/arch/arm/dts/stm32mp157.dtsi +++ b/arch/arm/dts/stm32mp157.dtsi @@ -20,7 +20,7 @@ dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 15a04ae927..9e1c9c0329 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -31,6 +31,7 @@ /* only needed for boot with TF-A, witout FIP support */ firmware { optee { + u-boot,dm-pre-reloc; compatible = "linaro,optee-tz"; method = "smc"; }; @@ -38,8 +39,10 @@
reserved-memory { u-boot,dm-spl; + u-boot,dm-pre-reloc;
optee@de000000 { + u-boot,dm-pre-reloc; reg = <0xde000000 0x02000000>; no-map; u-boot,dm-spl; @@ -61,117 +64,6 @@ status = "okay"; };
-&clk_hse { - st,digbypass; -}; - -&i2c4 { - u-boot,dm-pre-reloc; -}; - -&i2c4_pins_a { - u-boot,dm-pre-reloc; - pins { - u-boot,dm-pre-reloc; - }; -}; - -&pmic { - u-boot,dm-pre-reloc; -}; - -&rcc { - st,clksrc = < - CLK_MPU_PLL1P - CLK_AXI_PLL2P - CLK_MCU_PLL3P - CLK_PLL12_HSE - CLK_PLL3_HSE - CLK_PLL4_HSE - CLK_RTC_LSE - CLK_MCO1_DISABLED - CLK_MCO2_DISABLED - >; - - st,clkdiv = < - 1 /*MPU*/ - 0 /*AXI*/ - 0 /*MCU*/ - 1 /*APB1*/ - 1 /*APB2*/ - 1 /*APB3*/ - 1 /*APB4*/ - 2 /*APB5*/ - 23 /*RTC*/ - 0 /*MCO1*/ - 0 /*MCO2*/ - >; - - st,pkcs = < - CLK_CKPER_HSE - CLK_FMC_ACLK - CLK_QSPI_ACLK - CLK_ETH_DISABLED - CLK_SDMMC12_PLL4P - CLK_DSI_DSIPLL - CLK_STGEN_HSE - CLK_USBPHY_HSE - CLK_SPI2S1_PLL3Q - CLK_SPI2S23_PLL3Q - CLK_SPI45_HSI - CLK_SPI6_HSI - CLK_I2C46_HSI - CLK_SDMMC3_PLL4P - CLK_USBO_USBPHY - CLK_ADC_CKPER - CLK_CEC_LSE - CLK_I2C12_HSI - CLK_I2C35_HSI - CLK_UART1_HSI - CLK_UART24_HSI - CLK_UART35_HSI - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q - CLK_SAI4_PLL3Q - CLK_RNG1_LSI - CLK_RNG2_LSI - CLK_LPTIM1_PCLK1 - CLK_LPTIM23_PCLK3 - CLK_LPTIM45_LSE - >; - - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { - compatible = "st,stm32mp1-pll"; - reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { - compatible = "st,stm32mp1-pll"; - reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { - compatible = "st,stm32mp1-pll"; - reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -}; - &sdmmc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi index 06ef3a4095..9f9979dc5f 100644 --- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi @@ -4,3 +4,43 @@ */
#include "stm32mp157a-dk1-u-boot.dtsi" + +&optee { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&scmi0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&scmi0_clk { + u-boot,dm-pre-reloc; +}; + +&scmi0_reset { + u-boot,dm-pre-reloc; +}; + +&scmi0_shm { + u-boot,dm-pre-reloc; +}; + +&scmi1 { + status = "disabled"; + u-boot,dm-pre-reloc; +}; + +&scmi1_clk { + u-boot,dm-pre-reloc; +}; + +&scmi1_shm { + u-boot,dm-pre-reloc; +}; + +&scmi_sram { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 2bc92ef3ae..fb9300fcb1 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -99,3 +99,12 @@ pinctrl-2 = <&usart2_idle_pins_c>; status = "disabled"; }; + +&optee { + status = "okay"; +}; + +&scmi0 { + compatible = "linaro,scmi-optee"; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 408abaf52f..e2e1769d97 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -32,6 +32,8 @@ optee { compatible = "linaro,optee-tz"; method = "smc"; + u-boot,dm-pre-reloc; + status = "okay"; }; };
@@ -39,6 +41,7 @@ optee@fe000000 { reg = <0xfe000000 0x02000000>; no-map; + u-boot,dm-pre-reloc; }; }; #endif @@ -53,10 +56,6 @@ }; };
-&clk_hse { - st,digbypass; -}; - &i2c4 { u-boot,dm-pre-reloc; }; @@ -72,98 +71,6 @@ u-boot,dm-pre-reloc; };
-&rcc { - st,clksrc = < - CLK_MPU_PLL1P - CLK_AXI_PLL2P - CLK_MCU_PLL3P - CLK_PLL12_HSE - CLK_PLL3_HSE - CLK_PLL4_HSE - CLK_RTC_LSE - CLK_MCO1_DISABLED - CLK_MCO2_DISABLED - >; - - st,clkdiv = < - 1 /*MPU*/ - 0 /*AXI*/ - 0 /*MCU*/ - 1 /*APB1*/ - 1 /*APB2*/ - 1 /*APB3*/ - 1 /*APB4*/ - 2 /*APB5*/ - 23 /*RTC*/ - 0 /*MCO1*/ - 0 /*MCO2*/ - >; - - st,pkcs = < - CLK_CKPER_HSE - CLK_FMC_ACLK - CLK_QSPI_ACLK - CLK_ETH_DISABLED - CLK_SDMMC12_PLL4P - CLK_DSI_DSIPLL - CLK_STGEN_HSE - CLK_USBPHY_HSE - CLK_SPI2S1_PLL3Q - CLK_SPI2S23_PLL3Q - CLK_SPI45_HSI - CLK_SPI6_HSI - CLK_I2C46_HSI - CLK_SDMMC3_PLL4P - CLK_USBO_USBPHY - CLK_ADC_CKPER - CLK_CEC_LSE - CLK_I2C12_HSI - CLK_I2C35_HSI - CLK_UART1_HSI - CLK_UART24_HSI - CLK_UART35_HSI - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q - CLK_SAI4_PLL3Q - CLK_RNG1_LSI - CLK_RNG2_LSI - CLK_LPTIM1_PCLK1 - CLK_LPTIM23_PCLK3 - CLK_LPTIM45_LSE - >; - - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { - compatible = "st,stm32mp1-pll"; - reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { - compatible = "st,stm32mp1-pll"; - reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { - compatible = "st,stm32mp1-pll"; - reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -}; - &sdmmc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 6e89f88a17..eabf00f1fe 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -341,6 +341,11 @@ status = "okay"; };
+&scmi0 { + compatible = "linaro,scmi-optee"; + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 0e725498dd..9823d5d5ca 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -21,6 +21,20 @@ stdout-path = "serial0:115200n8"; };
+ clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + }; + led { compatible = "gpio-leds"; blue { diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi index b06a55a2fa..435846883f 100644 --- a/arch/arm/dts/stm32mp15xc.dtsi +++ b/arch/arm/dts/stm32mp15xc.dtsi @@ -10,8 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; + clocks = <&scmi0_clk CK_SCMI0_CRYP1>; + resets = <&scmi0_reset RST_SCMI0_CRYP1>; status = "disabled"; }; }; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 4cdaf13582..e02770b98e 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,31 @@
#define STM32MP1_LAST_CLK 232
+/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_PLL2_Q 5 +#define CK_SCMI0_PLL2_R 6 +#define CK_SCMI0_MPU 7 +#define CK_SCMI0_AXI 8 +#define CK_SCMI0_BSEC 9 +#define CK_SCMI0_CRYP1 10 +#define CK_SCMI0_GPIOZ 11 +#define CK_SCMI0_HASH1 12 +#define CK_SCMI0_I2C4 13 +#define CK_SCMI0_I2C6 14 +#define CK_SCMI0_IWDG1 15 +#define CK_SCMI0_RNG1 16 +#define CK_SCMI0_RTC 17 +#define CK_SCMI0_RTCAPB 18 +#define CK_SCMI0_SPI6 19 +#define CK_SCMI0_USART1 20 + +#define CK_SCMI1_PLL3_Q 0 +#define CK_SCMI1_PLL3_R 1 +#define CK_SCMI1_MCU 2 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index 702da37a2e..f3a0ed3178 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -106,4 +106,18 @@ #define GPIOJ_R 19785 #define GPIOK_R 19786
+/* SCMI reset domain identifiers */ +#define RST_SCMI0_SPI6 0 +#define RST_SCMI0_I2C4 1 +#define RST_SCMI0_I2C6 2 +#define RST_SCMI0_USART1 3 +#define RST_SCMI0_STGEN 4 +#define RST_SCMI0_GPIOZ 5 +#define RST_SCMI0_CRYP1 6 +#define RST_SCMI0_HASH1 7 +#define RST_SCMI0_RNG1 8 +#define RST_SCMI0_MDMA 9 +#define RST_SCMI0_MCU 10 +#define RST_SCMI0_MCU_HOLD_BOOT 11 + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */