Am 28.05.2014 12:16, schrieb Heiko Schocher:
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang.
As I've never seen this, yet: Any idea what goes wrong if this happens?
Thanks
Dirk
Signed-off-by: Heiko Schocher hs@denx.de Cc: Dirk Behme dirk.behme@gmail.com Cc: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com
drivers/spi/mxc_spi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index f3f029d..3cd93cf 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -212,6 +212,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, int nbytes = DIV_ROUND_UP(bitlen, 8); u32 data, cnt, i; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
int timeout;
debug("%s: bitlen %d dout 0x%x din 0x%x\n", __func__, bitlen, (u32)dout, (u32)din);
@@ -272,9 +273,12 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
- timeout = 10000; /* Wait until the TC (Transfer completed) bit is set */
- while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0)
;
while (timeout && ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0)) {
timeout--;udelay(10);}
/* Transfer completed, clear any pending request */ reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);