--- Ursprüngliche Nachricht --- Von: Steven Scholz steven.scholz@imc-berlin.de An: Anders Larsen alarsen@rea.de Kopie: "Patrick .." oc3an@gmx.net, u-boot-users@lists.sourceforge.net Betreff: Re: [U-Boot-Users] AT91RM9200 Errata (Was: CSB637 support - big bug..) Datum: Wed, 24 Aug 2005 11:01:30 +0200
Patrick,
This is not the main problem however,
In the AT91RM9200 initialisation code, PMC_MCKR is written incorrectly. This register *MUST* be written in two separate steps (see the errata sheet for the AT91RM9200 for more details). In my case i write 0x201, followed by 0x202.
How did you do that? Do you wait some time between the first and the second write?
-- Steven
SF.Net email is Sponsored by the Better Software Conference & EXPO September 19-22, 2005 * San Francisco, CA * Development Lifecycle Practices Agile & Plan-Driven Development * Managing Projects & Teams * Testing & QA Security * Process Improvement & Measurement * http://www.sqe.com/bsce5sf _______________________________________________ U-Boot-Users mailing list U-Boot-Users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users
No need to wait between the writes.
This fix is quite simple to implement. in lowlevel_init.S edit the values for MCKR (as shown below). You also need to modify the length of the assembly loop some lines above which iterates through this list (also shown below). This length should really be calculated (but it works).
Then define MCKR_VAL0 as the first value to be written and MCKR_VAL1 as the second in the includes/common/csb637.h file.
Hope this helps,
-Patrick
SMRDATA: .word MC_PUIA .word MC_PUIA_VAL .word MC_PUP .word MC_PUP_VAL .word MC_PUER .word MC_PUER_VAL .word MC_ASR .word MC_ASR_VAL .word MC_AASR .word MC_AASR_VAL .word EBI_CFGR .word EBI_CFGR_VAL .word SMC2_CSR .word SMC2_CSR_VAL .word PLLAR .word PLLAR_VAL .word PLLBR .word PLLBR_VAL .word MCKR // Edited by Patrick .word MCKR_VAL0 // Edited by Patrick .word MCKR // Edited by Patrick .word MCKR_VAL1 // Edited by Patrick /* SMRDATA is 88 bytes long */ /* here there's a delay of 100 */
/* memory control configuration */ /* this isn't very elegant, but what the heck */ ldr r0, =SMRDATA ldr r1, _MTEXT_BASE sub r0, r0, r1 add r2, r0, #88 // Edited by Patrick