Hi Nishanth, On Monday 17 August 2015 08:01 PM, menon.nishanth@gmail.com wrote:
On Mon, Aug 17, 2015 at 9:24 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
Currently u-boot stack is defined at the beginning of MSMC RAM. This is a problem for uart boot mode as ROM downloads directly to starting of MSMC RAM. Fixing it by moving stack to the end of u-boot section and shifting SYS_TEXT_BASE to the start of MSMC RAM. Updated division of MSMC RAM is shown below: ----------------------------------------- | | | | | U-Boot text |U-Boot | SPL text | | download | Stack | Download + | | | | SPL_BSS + | | | | SPL_STACK | ----------------------------------------- [1] [2] [3] [4]
[1] SYS_TEXT_BASE (Start of MSMC RAM) [2] SPL_TEXT_BASE - GBL_DATA_SIZE [3] SPL_TEXT_BASE [4] END of SPL
[1] + [2] is at least 1M on all platforms, so no chance of overlap.
Reviewed-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
include/configs/ti_armv7_keystone2.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index b441590..58c98ce 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -20,7 +20,7 @@ /* SoC Configuration */ #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_TEXT_BASE 0x0c001000 +#define CONFIG_SYS_TEXT_BASE 0x0c000000 #define CONFIG_SPL_TARGET "u-boot-spi.gph" #define CONFIG_SYS_DCACHE_OFF
@@ -29,7 +29,7 @@ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ GENERATED_GBL_DATA_SIZE)
/* SPL SPI Loader Configuration */
This change is great. Now that this patch is done, I might like to see the documentation of uart download added in as well - the sequence is not really straight forward without documentation to follow
Patch 5/5 does the update in the README.
Thanks and regards, Lokesh
Regards, Nishanth Menon