Hi Mauro,
(This is my personal mail account.)
Please don't copy and paste from my out-of-date patches.
You are copying code from v1 https://patchwork.ozlabs.org/patch/1154190/
which has already been replaced by v3 https://patchwork.ozlabs.org/patch/1167073/
SInce v3 is the mainline version, you should drop all modifications from v1 and rebase your patch based on v3. Basically you should drop all modifications of arch/mips/dts/mt7628a.dtsi.
I'll give comments on your next patch.
Thanks, Weijie
Mauro Condarelli mc5686@mclink.it 于2020年1月28日周二 上午1:46写道：
I just trimmed too much. This is also the cause of MMC/SD misbehavior (missing interrupt). I will send another patch *after* some serious testing. Regards Mauro
On 1/27/20 1:41 PM, Stefan Roese wrote:
On 25.01.20 22:12, Mauro Condarelli wrote:
Small patch series to add support for VoCore/VoCore2 board.
VoCore is open hardware and runs OpenWrt/LEDE. It has WIFI, USB, UART, 20+ GPIOs but is only one inch square. It will help you to make a smart house, study embedded system or even make the tiniest router in the world.
Details about this SoM can be found at "https://vocore.io/v2.html".
Signed-off-by: Mauro Condarelli mc5686@mclink.it
Changes in v3:
- based on top of Weijie Gao patchset: "[v3,xx/20]Refactor the architecture parts of mt7628"
Changes in v2:
Removed some dead code
Changed Author to my full name (no nick)
Removed unwanted fixup to .dts generation (not my call).
Fixed commit message
Fixed various variables/filenames to include Vendor name
Changed Vendor name (Vonger -> Vocore)
MAINTAINERS | 1 + arch/mips/dts/Makefile | 1 + arch/mips/dts/mt7628a.dtsi | 56 ++++------------- arch/mips/dts/vocore_vocore2.dts | 76 +++++++++++++++++++++++ arch/mips/mach-mtmips/Kconfig | 8 +++ board/vocore/vocore2/Kconfig | 12 ++++ board/vocore/vocore2/Makefile | 3 + board/vocore/vocore2/board.c | 33 ++++++++++ configs/vocore2_defconfig | 100 +++++++++++++++++++++++++++++++ include/configs/vocore2.h | 66 ++++++++++++++++++++ 10 files changed, 311 insertions(+), 45 deletions(-) create mode 100644 arch/mips/dts/vocore_vocore2.dts create mode 100644 board/vocore/vocore2/Kconfig create mode 100644 board/vocore/vocore2/Makefile create mode 100644 board/vocore/vocore2/board.c create mode 100644 configs/vocore2_defconfig create mode 100644 include/configs/vocore2.h
diff --git a/MAINTAINERS b/MAINTAINERS index 7d2729dfb0..aef0f4a26d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1,3 +1,4 @@ +source /home/mcon/.basheditor/remote-debugging-v1.sh localhost 33333 #BASHEDITOR-TMP-REMOTE-DEBUGGING-END|Origin line: Descriptions of section entries: P: Person (obsolete) diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index cbd0c8bc8b..f711e9fb59 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -23,6 +23,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +dtb-$(CONFIG_BOARD_VOCORE2) += vocore_vocore2.dtb dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 6baa63add3..3d4f29e0c5 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -7,6 +7,11 @@ #size-cells = <1>; compatible = "ralink,mt7628a-soc";
- resetc: reset-controller {
compatible = "ralink,rt2880-reset";#reset-cells = <1>;- };
cpus { #address-cells = <1>; #size-cells = <0>;@@ -61,6 +66,12 @@ u-boot,dm-pre-reloc; };
clkgate: clkgate@0x30 {reg = <0x30 0x4>;compatible = "mediatek,mediatek,mt7628-clk";#clock-cells = <1>;};If these changes are really necessary, then please submit them as a separate patch with a description, why they are needed.
rstctrl: rstctrl@0x34 { reg = <0x34 0x4>; compatible = "mediatek,mtmips-reset";@@ -228,32 +239,6 @@ resets = <&rstctrl MT7628_TIMER_RST>; reset-names = "wdt";
interrupt-parent = <&intc>;interrupts = <24>;};intc: interrupt-controller@200 {compatible = "ralink,rt2880-intc";reg = <0x200 0x100>;interrupt-controller;#interrupt-cells = <1>;resets = <&rstctrl MT7628_INT_RST>;reset-names = "intc";interrupt-parent = <&cpuintc>;interrupts = <2>;ralink,intc-registers = <0x9c 0xa00x6c 0xa40x80 0x78>;};memory-controller@300 {compatible = "ralink,mt7620a-memc";reg = <0x300 0x100>; };Why do you remove these DT nodes? Please drop these changes.
gpio@600 {@@ -266,9 +251,6 @@ resets = <&rstctrl MT7628_PIO_RST>; reset-names = "pio";
interrupt-parent = <&intc>;interrupts = <6>;gpio0: bank@0 { reg = <0>; compatible = "mtk,mt7621-gpio-bank";@@ -316,9 +298,6 @@ resets = <&rstctrl MT7628_UART0_RST>; reset-names = "uart0";
interrupt-parent = <&intc>;interrupts = <20>;reg-shift = <2>; };
interrupt-parent = <&intc>;interrupts = <21>;reg-shift = <2>; };
interrupt-parent = <&intc>;interrupts = <22>;reg-shift = <2>; }; };@@ -366,8 +339,6 @@ resets = <&rstctrl MT7628_EPHY_RST>; reset-names = "ephy";
syscon = <&sysc>; }; usb_phy: usb-phy@10120000 {@@ -376,8 +347,6 @@ #phy-cells = <0>;
ralink,sysctl = <&sysc>;resets = <&rstctrl MT7628_UPHY_RST>; reset-names = "phy";interrupt-parent = <&intc>;interrupts = <18>; }; mmc: mmc@10130000 {diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts new file mode 100644 index 0000000000..b8fd87a3e9 --- /dev/null +++ b/arch/mips/dts/vocore_vocore2.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019 Mauro Condarelli mc5686@mclink.it
- */
+/dts-v1/;
+#include "mt7628a.dtsi" +#include <dt-bindings/gpio/gpio.h>
+/ {
- compatible = "vocore,vocore2", "ralink,mt7628a-soc";
- model = "VoCore2";
- aliases {
serial0 = &uart2;spi0 = &spi0;- };
- memory@0 {
device_type = "memory";reg = <0x0 0x08000000>;- };
- leds {
compatible = "gpio-leds";power {label = "vocore:power";gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;default-state = "off";};- };
- chosen {
bootargs = "console=ttyS2,115200";stdout-path = &uart2;- };
+};
+&pinctrl {
- state_default: pin_state {
p0led {groups = "p0led_a";function = "led";};- };
+};
+&uart2 {
- status = "okay";
+};
+&spi0 {
- status = "okay";
- nor0: spi-flash@0 {
#address-cells = <1>;#size-cells = <1>;compatible = "jedec,spi-nor";spi-max-frequency = <25000000>;reg = <0>;- };
+};
+ð {
- pinctrl-names = "default";
- pinctrl-0 = <&ephy_iot_mode>;
- mediatek,poll-link-phy = <0>;
+};
+&mmc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&sd_iot_mode>;
- pinctrl-1 = <&sd_iot_mode>;
+}; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index bcd635f438..489e466daf 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -83,6 +83,13 @@ config BOARD_MT7628_RFB SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host, 1 SDXC, 1 PCIe socket and JTAG pins. +config BOARD_VOCORE2
- bool "VoCore2"
- depends on SOC_MT7628
- help
VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAMand 16 MiB of flash (SPI).- endchoice config SPL_UART2_SPIS_PINMUX
@@ -96,5 +103,6 @@ config SPL_UART2_SPIS_PINMUX source "board/gardena/smart-gateway-mt7688/Kconfig" source "board/mediatek/mt7628/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" +source "board/vocore/vocore2/Kconfig" endmenu diff --git a/board/vocore/vocore2/Kconfig b/board/vocore/vocore2/Kconfig new file mode 100644 index 0000000000..baeff31b69 --- /dev/null +++ b/board/vocore/vocore2/Kconfig @@ -0,0 +1,12 @@ +if BOARD_VOCORE2
+config SYS_BOARD
- default "vocore2"
+config SYS_VENDOR
- default "vocore"
+config SYS_CONFIG_NAME
- default "vocore2"
+endif diff --git a/board/vocore/vocore2/Makefile b/board/vocore/vocore2/Makefile new file mode 100644 index 0000000000..70cd7a8e56 --- /dev/null +++ b/board/vocore/vocore2/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+
+obj-y += board.o diff --git a/board/vocore/vocore2/board.c b/board/vocore/vocore2/board.c new file mode 100644 index 0000000000..d387715d14 --- /dev/null +++ b/board/vocore/vocore2/board.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2019 Mauro Condarelli mc5686@mclink.it
- Note: this is largely copied from:
board/seeed/linkit_smart_7688/board.c
Copyright (C) 2018 Stefan Roese <sr@denx.de>- */
+#include <common.h> +#include <asm/io.h>
+#define MT76XX_GPIO1_MODE 0x10000060
+void board_debug_uart_init(void) +{
- void __iomem *gpio_mode;
- /* Select UART2 mode instead of GPIO mode (default) */
- gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100);
- clrbits_le32(gpio_mode, GENMASK(27, 26));
+}
+int board_early_init_f(void) +{
- /*
* The pin muxing of UART2 also needs to be done, if debug uart* is not enabled. So we need to call this function here as well.*/- board_debug_uart_init();
- return 0;
+} diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig new file mode 100644 index 0000000000..04c7a6a6f5 --- /dev/null +++ b/configs/vocore2_defconfig @@ -0,0 +1,100 @@ +CONFIG_MIPS=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_ARCH_MTMIPS=y +CONFIG_BOARD_VOCORE2=y +CONFIG_SPL_UART2_SPIS_PINMUX=y +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BOOT_GET_KBD=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_BOOTARGS=y +CONFIG_LOGLEVEL=8 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_VERSION_VARIABLE=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTOBOOT is not set +CONFIG_CMD_LICENSE=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="spi0.0:312k(u-boot),4k(env),4k(factory),2368k(kernel),-(filesystem)"
+# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_INTERFACE="mmc" +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set +CONFIG_SPL_DM=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +# CONFIG_DM_ETH is not set +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=3 +CONFIG_SPI=y +CONFIG_MT7621_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +CONFIG_FS_EXT4=y +CONFIG_LZMA=y +CONFIG_LZO=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h new file mode 100644 index 0000000000..602a78d0d5 --- /dev/null +++ b/include/configs/vocore2.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019 Mauro Condarelli mc5686@mclink.it
- */
+#ifndef __VOCORE2_CONFIG_H__ +#define __VOCORE2_CONFIG_H__
+/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
+/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000
+/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0
+/* Serial SPL */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CONFIG_CONS_INDEX 3
+#endif
+/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }+/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000
+/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512
Nitpicking: Again, I suspect that checkpatch will complain about this alignment / indentation. Please change.
+/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+/* Environment settings */ +#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) +#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#endif
Is this really needed?
+#endif//__VOCORE2_CONFIG_H__
Again, here as well. checkpatch will complain about the missing spaces.
Thanks, Stefan