From: Wan Yee Lau wan.yee.lau@intel.com
Update Kconfig for new platform Agilex7 M-series.
Signed-off-by: Wan Yee Lau wan.yee.lau@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com Signed-off-by: Tingting Meng tingting.meng@intel.com --- arch/arm/Kconfig | 4 +++- arch/arm/mach-socfpga/Kconfig | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 56e190adf6..f68b680d82 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -32,7 +32,9 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 + default 400000000 if ARCH_SOCFPGA && ARM64 && !TARGET_SOCFPGA_AGILEX7M + default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 && \ + TARGET_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1008232cac..2ca6336f21 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -59,6 +59,18 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64
+config TARGET_SOCFPGA_AGILEX7M + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV2 + select NCORE_CACHE + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF @@ -139,6 +151,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX
+config TARGET_SOCFPGA_AGILEX7M_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" + select TARGET_SOCFPGA_AGILEX7M + config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 @@ -216,6 +232,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice
config SYS_BOARD + default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -238,6 +255,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK @@ -261,6 +279,7 @@ config SYS_SOC default "socfpga"
config SYS_CONFIG_NAME + default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1