Each phase is given a separate 'is_dtr' field so mixed protocols like 4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav p.yadav@ti.com --- drivers/spi/spi-mem.c | 24 ++++++++++++++++++++++++ include/spi-mem.h | 8 ++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index e900c997bd..218496d8d2 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -104,6 +104,16 @@ void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data); #endif /* __UBOOT__ */
+static int spi_check_dtr_req(struct spi_slave *slave, bool tx) +{ + u32 mode = slave->mode; + + if ((tx && (mode & SPI_TX_DTR)) || (!tx && (mode & SPI_RX_DTR))) + return 0; + + return -ENOTSUPP; +} + static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx) { u32 mode = slave->mode; @@ -158,6 +168,20 @@ bool spi_mem_default_supports_op(struct spi_slave *slave, op->data.dir == SPI_MEM_DATA_OUT)) return false;
+ if (op->cmd.is_dtr && spi_check_dtr_req(slave, true)) + return false; + + if (op->addr.is_dtr && spi_check_dtr_req(slave, true)) + return false; + + if (op->dummy.is_dtr && + spi_check_dtr_req(slave, true)) + return false; + + if (op->data.is_dtr && + spi_check_dtr_req(slave, op->data.dir == SPI_MEM_DATA_OUT)) + return false; + return true; } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); diff --git a/include/spi-mem.h b/include/spi-mem.h index 36814efa86..1ae5f2b302 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -72,6 +72,7 @@ enum spi_mem_data_dir { * struct spi_mem_op - describes a SPI memory operation * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode + * @cmd.is_dtr: whether the command opcode should be sent in DTR mode or not * @addr.nbytes: number of address bytes to send. Can be zero if the operation * does not need to send an address * @addr.buswidth: number of IO lines used to transmit the address cycles @@ -79,11 +80,14 @@ enum spi_mem_data_dir { * Note that only @addr.nbytes are taken into account in this * address value, so users should make sure the value fits in the * assigned number of bytes. + * @addr.is_dtr: whether the address should be sent in DTR mode or not * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can * be zero if the operation does not require dummy bytes * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes + * @dummy.is_dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dir: direction of the transfer + * @data.is_dtr: whether the data should be sent in DTR mode or not * @data.buf.in: input buffer * @data.buf.out: output buffer */ @@ -91,23 +95,27 @@ struct spi_mem_op { struct { u8 buswidth; u8 opcode; + bool is_dtr; } cmd;
struct { u8 nbytes; u8 buswidth; u64 val; + bool is_dtr; } addr;
struct { u8 nbytes; u8 buswidth; + bool is_dtr; } dummy;
struct { u8 buswidth; enum spi_mem_data_dir dir; unsigned int nbytes; + bool is_dtr; /* buf.{in,out} must be DMA-able. */ union { void *in;