BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore.
To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- Dependent on nand_spl patch set(0001-0006) http://patchwork.ozlabs.org/patch/229892/ to be present
README | 7 +++++++ arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ arch/powerpc/include/asm/fsl_law.h | 5 +++++ board/freescale/bsc9131rdb/law.c | 4 ++++ board/freescale/bsc9131rdb/tlb.c | 6 ++++++ include/configs/BSC9131RDB.h | 5 +++++ 6 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/README b/README index c4ad69d..b38e07a 100644 --- a/README +++ b/README @@ -423,6 +423,13 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround.
+ CONFIG_SYS_FSL_DSP_M2_RAM_ADDR + This value denotes start offset of M2 memory + which is directly connected to the DSP core. + + CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT + This value denotes start offset of DSP CCSR space. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 71f143e..bd4cbf1 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -488,6 +488,8 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 +#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index f9cec8e..5505d6f 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -80,11 +80,16 @@ enum law_trgt_if { #ifndef CONFIG_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif +#if defined(CONFIG_BSC9131) + LAW_TRGT_IF_OCN_DSP = 0x03, +#else #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif +#endif LAW_TRGT_IF_LBC = 0x04, LAW_TRGT_IF_CCSR = 0x08, + LAW_TRGT_IF_DSP_CCSR = 0x09, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, LAW_TRGT_IF_RIO_2 = 0x0d, diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c index 201c147..0432780 100644 --- a/board/freescale/bsc9131rdb/law.c +++ b/board/freescale/bsc9131rdb/law.c @@ -26,6 +26,10 @@
struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DSP_CCSR), + SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M, + LAW_TRGT_IF_OCN_DSP), };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index e6cb37a..c802ed4 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -52,6 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1),
+ /* CCSRBAR (DSP) */ + SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, + CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 9a62c8c..4ea74e4 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -153,16 +153,21 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ +/* DSP CCSRBAR */ +#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT +#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
/* * Memory map * * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M + * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M *