
18 Jul
2019
18 Jul
'19
1:45 p.m.
Hi Peng and Ye Li,
On Wed, May 15, 2019 at 6:56 AM Peng Fan peng.fan@nxp.com wrote:
This patchset is to upstream ddr script from NXP vendor tree, witout this patchset, the ULP B0 EVK board could not boot up.
Ye Li (5): mx7ulp: Fix APLL num and denom setting issue mx7ulp_evk: Update LPDDR3 script mx7ulp_evk: Change APLL and its PFD0 frequencies mx7ulp: Select the SCG1 APLL PFD as a system clock source mx7ulp_evk: Update DDR freq to 352.8Mhz for ULP B0
This series fixes the boot issue on a mx7ulp evk board with B0 silicon:
Tested-by: Fabio Estevam festevam@gmail.com
Stefano,
Could you please consider it for 2019.10 inclusion?
Thanks