Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros.
Signed-off-by: York Sun york.sun@nxp.com ---
arch/powerpc/cpu/mpc85xx/Kconfig | 5 +++++ arch/powerpc/cpu/mpc85xx/Makefile | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 2 +- arch/powerpc/include/asm/config_mpc85xx.h | 2 +- arch/powerpc/include/asm/immap_85xx.h | 2 +- drivers/qe/uec.c | 10 +++++----- include/configs/p1_p2_rdb_pc.h | 1 - include/configs/p1_twr.h | 1 - scripts/config_whitelist.txt | 1 - 9 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 62c0dec..90777db 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -156,6 +156,7 @@ config TARGET_P1025RDB bool "Support P1025RDB" select SUPPORT_SPL select SUPPORT_TPL + select ARCH_P1025
config TARGET_P2020RDB bool "Support P2020RDB-PC" @@ -164,6 +165,7 @@ config TARGET_P2020RDB
config TARGET_P1_TWR bool "Support p1_twr" + select ARCH_P1025
config TARGET_P2041RDB bool "Support P2041RDB" @@ -301,6 +303,9 @@ config ARCH_P1023 config ARCH_P1024 bool
+config ARCH_P1025 + bool + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 239cf41..a3fba03 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -79,7 +79,7 @@ obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o -obj-$(CONFIG_P1025) += p1021_serdes.o +obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o obj-$(CONFIG_P2010) += p2020_serdes.o obj-$(CONFIG_P2020) += p2020_serdes.o obj-$(CONFIG_PPC_P2041) += p2041_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 8155620..38a28a8 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -596,7 +596,7 @@ void get_sys_info(sys_info_t *sys_info) #endif
#ifdef CONFIG_QE -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) sys_info->freq_qe = sys_info->freq_systembus; #else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index dffc222..6874b54 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -265,7 +265,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */ -#elif defined(CONFIG_P1025) +#elif defined(CONFIG_ARCH_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b0f81ec..f8a6a78 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2488,7 +2488,7 @@ typedef struct ccsr_gur { u8 res11a[76]; par_io_t qe_par_io[7]; u8 res11b[1600]; -#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025) +#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) u8 res11a[12]; u32 iovselsr; u8 res11b[60]; diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 2bb630d..b3af707 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -567,7 +567,7 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv;
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII managment signals */ @@ -578,7 +578,7 @@ static void phy_change(struct eth_device *dev) /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info);
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* * QE12 is muxed with LBCTL, it needs to be released for enabling * LBCTL signal for LBC usage. @@ -1193,14 +1193,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) { -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE9 and QE12 need to be set for enabling QE MII managment signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); @@ -1232,7 +1232,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1);
-#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE12 needs to be released for enabling LBCTL signal*/ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 119bd10..3320a7e 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -128,7 +128,6 @@ #if defined(CONFIG_TARGET_P1025RDB) #define CONFIG_BOARDNAME "P1025RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1025 #define CONFIG_QE #define CONFIG_SLIC
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index ef32181..c122f8e 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -12,7 +12,6 @@
#if defined(CONFIG_TWR_P1025) #define CONFIG_BOARDNAME "TWR-P1025" -#define CONFIG_P1025 #define CONFIG_PHY_ATHEROS #define CONFIG_QE #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 44376ab..e4dcd0b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3383,7 +3383,6 @@ CONFIG_OS2_ENV_ADDR CONFIG_OS_ENV_ADDR CONFIG_OTHBOOTARGS CONFIG_OVERWRITE_ETHADDR_ONCE -CONFIG_P1025 CONFIG_P2020 CONFIG_P2041RDB CONFIG_P3041DS