On 12/17/2013 12:55 AM, Priyanka Jain wrote:
Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock.
So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock
DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
Changes for v4: Updated README with CONFIG_SYS_FSL_SINGLE_SOURCE_CLK description.
Changes for v3: Incorporated York's comment to move declaration to beginning of function.
Changes for v2: Incorporated York's comment to separate out DDR_CLK_FREQ and SINGLE_SOURCE_CLK code
Applied to u-boot-mpc85xx/master. Thanks.
York