Hi Christian,
On 23 May 2018 at 06:00, Christian Gmeiner christian.gmeiner@gmail.com wrote:
If u-boot gets used as coreboot payload all pci resources got
U-Boot
(please use this consistently)
assigned by coreboot. If a dts without any pci ranges gets used the dm is not able to access pci device memory. To get things working make use of a 1:1 mapping for bus <-> phy addresses.
This change makes it possible to get the e1000 u-boot driver working on a sandybridge device where u-boot is used as coreboot payload.
Signed-off-by: Christian Gmeiner christian.gmeiner@gmail.com
drivers/pci/pci-uclass.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 416444a230..9cec619bb2 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1175,6 +1175,11 @@ static int _dm_pci_bus_to_phys(struct udevice *ctlr, struct pci_region *res; int i;
if (hose->region_count == 0) {
Or just if (!hose->region_count)
Please add a comment as to the case you are covering here. How come the mapping will be 1:1? Is that guaranteed?
*pa = bus_addr;return 0;}for (i = 0; i < hose->region_count; i++) { res = &hose->regions[i];@@ -1238,6 +1243,11 @@ int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, ctlr = pci_get_controller(dev); hose = dev_get_uclass_priv(ctlr);
if (hose->region_count == 0) {*ba = phys_addr;return 0;}for (i = 0; i < hose->region_count; i++) { res = &hose->regions[i];-- 2.17.0
Regards, Simon