Thanks, Simon. I'll take it in to u-boot-tegra/master for the next PR.
-----Original Message----- From: sjg@google.com [mailto:sjg@google.com] On Behalf Of Simon Glass Sent: Wednesday, June 14, 2017 4:32 AM To: Peter Chubb Peter.Chubb@data61.csiro.au Cc: U-Boot Mailing List u-boot@lists.denx.de; Tom Warren TWarren@nvidia.com; Stephen Warren swarren@wwwdotorg.org; Jaehoon Chung jh80.chung@samsung.com; Stephen Warren swarren@nvidia.com Subject: Re: [PATCH] tegra: mmc: Set the bus width correctly
Hi,
On 7 June 2017 at 22:03, Peter.Chubb@data61.csiro.au wrote:
> "Simon" == Simon Glass sjg@chromium.org writes:
Simon> The driver currently does not reset bit 5 of the hostctl Simon> register even if the MMC stack requests it. Then means that Simon> once a bus width of 8 is selected it is not possible to change Simon> it back to 1. This breaks 'mmc rescan' which needs to start off Simon> with a bus width of 1.
Simon> The problem was surfaced by enabling CONFIG_DM_MMC_OPS on Simon> tegra. Without this option the MMC stack fully reinits the Simon> driver on a 'mmc rescan'. But with this option driver model Simon> does not re-probe a driver once it has been probed once.
Simon> Fix the driver to honour the request.
Simon> Signed-off-by: Simon Glass sjg@chromium.org ---
Tested-by: Peter Chubb peter.chubb@data61.csiro.au
Simon> drivers/mmc/tegra_mmc.c | 2 +- 1 file changed, 1 insertion(+), Simon> 1 deletion(-)
Simon> diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c Simon> index 338e42b528..7d945a172e 100644 --- Simon> a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ Simon> -438,7 +438,7 @@ static int tegra_mmc_set_ios(struct udevice Simon> *dev) else if (mmc->bus_width == 4) ctrl |= (1 << 1); else - Simon> ctrl &= ~(1 << 1); + ctrl &= ~(1 << 1 | 1 << 5);
Simon> writeb(ctrl, &priv->reg->hostctl); debug("mmc_set_ios: Simon> hostctl = %08X\n", ctrl); -- 2.13.0.506.g27d5fe0cd-goog
Thanks for testing this.
Tom please note this is a bug fix.
- Simon
-- nvpublic