This processor is most similar to the MPC8309, but lacks PCI.
Signed-off-by: Matevz Langus <matevz.langus at borea.si> --- Changes for v2: - Remove invalid Threads from QE SNUM allocation table for MPC8306 and MPC8309 to be in line with Freescale QEIWRM 4.4
arch/powerpc/cpu/mpc83xx/cpu.c | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 4 +++ arch/powerpc/cpu/mpc83xx/speed.c | 24 ++++++++++------ arch/powerpc/include/asm/global_data.h | 2 +- arch/powerpc/include/asm/immap_83xx.h | 52 +++++++++++++++++++++++++ +++++++-- arch/powerpc/include/asm/immap_qe.h | 2 +- drivers/qe/qe.c | 10 +++++-- include/mpc83xx.h | 9 +++--- 8 files changed, 85 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/ cpu.c index cc20234..13fd502 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -55,6 +55,7 @@ int checkcpu(void) char name[15]; u32 partid; } cpu_type_list [] = { + CPU_TYPE_ENTRY(8306), CPU_TYPE_ENTRY(8308), CPU_TYPE_ENTRY(8309), CPU_TYPE_ENTRY(8311), diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/ mpc83xx/cpu_init.c index 5153351..8beefc1 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -334,7 +334,11 @@ void cpu_init_f (volatile immap_t * im) struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
/* Configure interface. */ +#ifdef CONFIG_MPC8306 + setbits_be32(&ehci->control, REFSEL_16MHZ | PHY_CLK_SEL_ULPI); +#else setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); +#endif
/* Wait for clock to stabilize */ do { diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/ mpc83xx/speed.c index 6be0e3a..7c2a3bd 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -105,7 +105,7 @@ int get_clocks(void) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u32 usbdr_clk; #endif #ifdef CONFIG_MPC834x @@ -122,7 +122,7 @@ int get_clocks(void) #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) u32 enc_clk; #endif u32 lbiu_clk; @@ -166,7 +166,11 @@ int get_clocks(void) }
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; +#if defined(CONFIG_MPC8306) + csb_clk = CONFIG_83XX_CLKIN * spmf; +#else csb_clk = pci_sync_in * (1 + clkin_div) * spmf; +#endif
sccr = im->clk.sccr;
@@ -267,7 +271,7 @@ int get_clocks(void) return -6; } #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: enc_clk = 0; @@ -338,7 +342,7 @@ int get_clocks(void) i2c1_clk = sdhc_clk; #elif defined(CONFIG_MPC837x) i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) i2c1_clk = csb_clk; #endif #if !defined(CONFIG_MPC832x) @@ -458,7 +462,11 @@ int get_clocks(void) #if defined(CONFIG_QE) qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT; qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT; +#if defined(CONFIG_MPC8306) + qe_clk = (CONFIG_83XX_QE_CLKIN * qepmf) / (1 + qepdf); +#else qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); +#endif brg_clk = qe_clk / 2; #endif
@@ -468,7 +476,7 @@ int get_clocks(void) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) gd->arch.usbdr_clk = usbdr_clk; #endif #if defined(CONFIG_MPC834x) @@ -485,7 +493,7 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) gd->arch.i2c2_clk = i2c2_clk; #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) gd->arch.enc_clk = enc_clk; #endif gd->arch.lbiu_clk = lbiu_clk; @@ -555,7 +563,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->arch.mem_sec_clk)); #endif -#if !defined(CONFIG_MPC8309) +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) printf(" SEC: %-4s MHz\n", strmhz(buf, gd->arch.enc_clk)); #endif @@ -581,7 +589,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) strmhz(buf, gd->arch.tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); -#elif defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->arch.usbdr_clk)); #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/ include/asm/global_data.h index c02447f..f5341eb 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -51,7 +51,7 @@ struct arch_global_data { u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; -# elif defined(CONFIG_MPC8309) +# elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u32 usbdr_clk; # endif # if defined(CONFIG_MPC834x) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/ include/asm/immap_83xx.h index 8ac13fc..127352a 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -78,7 +78,7 @@ typedef struct sysconf83xx { #else u32 pecr2; /* PCI Express control register 2 */ #endif -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u32 can_dbg_ctrl; u32 res9a; u32 gpr1; @@ -715,7 +715,7 @@ typedef struct serdes83xx { * On Chip ROM */ typedef struct rom83xx { -#if defined(CONFIG_MPC8309) +#if defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) u8 mem[0x8000]; #else u8 mem[0x10000]; @@ -983,6 +983,54 @@ typedef struct immap { u8 res8[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; +#elif defined(CONFIG_MPC8306) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[2]; /* General purpose I/O module */ + u8 res0[0x500]; + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + qepio83xx_t qepio; /* QE Parallel I/O ports */ + u8 res1[0x800]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x200]; + duart83xx_t duart1[2]; /* DUART */ + u8 res4[0x500]; + fsl_lbc_t im_lbc; /* Local Bus Controller Registers */ + u8 res5[0x1000]; + u8 spi[0x100]; + u8 res6[0xf00]; + dma83xx_t dma; /* DMA */ + u8 res7[0x100]; + ios83xx_t ios; /* Sequencer (IOS) */ + u8 res8[0x13B00]; + u8 can1[0x1000]; /* Flexcan 1 */ + u8 can2[0x1000]; /* Flexcan 2 */ + u8 res9[0x5000]; + usb83xx_t usb; + u8 res10[0x5000]; + u8 can3[0x1000]; /* Flexcan 3 */ + u8 can4[0x1000]; /* Flexcan 4 */ + u8 res11[0x1000]; + u8 dma1[0x2000]; /* DMA */ + sdhc83xx_t sdhc; /* SDHC Controller */ + u8 res12[0xC1000]; + rom83xx_t rom; /* On Chip ROM */ + u8 res13[0x8000]; + u8 qe[0x100000]; /* QE block */ + u8 res14[0xE00000]; +} immap_t; #elif defined(CONFIG_MPC8309) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/ include/asm/immap_qe.h index f0b989a..b42fe62 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -20,7 +20,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309) +#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8306) || defined(CONFIG_MPC8309) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 5fd2135..a84b1b5 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -114,8 +114,8 @@ static void qe_sdma_init(void) * we just need to know what the SNUMs are for the threads. */ static u8 thread_snum[] = { -/* Evthreads 16-29 are not supported in MPC8309 */ -#if !defined(CONFIG_MPC8309) +/* Evthreads 16-29 are not supported in MPC8306 and MPC8309 */ +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, @@ -124,11 +124,15 @@ static u8 thread_snum[] = { 0x88, 0x89, 0x98, 0x99, 0xa8, 0xa9, 0xb8, 0xb9, 0xc8, 0xc9, 0xd8, 0xd9, - 0xe8, 0xe9, 0x08, 0x09, + 0xe8, 0xe9 +/* Threads listed bellow are not available on MPC8306 and MPC8309 */ +#if !defined(CONFIG_MPC8306) && !defined(CONFIG_MPC8309) + , 0x08, 0x09, 0x18, 0x19, 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59, 0x68, 0x69, 0x78, 0x79, 0x80, 0x81 +#endif };
static void qe_snums_init(void) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index b295d6d..5744b95 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -73,6 +73,7 @@ #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
+#define SPR_8306 0x8110 #define SPR_8308 0x8100 #define SPR_8309 0x8110 #define SPR_831X_FAMILY 0x80B @@ -215,7 +216,7 @@ #define SICRH_UC2E1OBI 0x00000002 #define SICRH_UC2E2OBI 0x00000001
-#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8306) /* SICRL bits - MPC832x specific */ #define SICRL_LDP_LCS_A 0x80000000 #define SICRL_IRQ_CKS 0x20000000 @@ -600,7 +601,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) || defined(CONFIG_MPC8306) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -646,7 +647,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_MPC8306) || defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_2 0x00000000 @@ -993,7 +994,7 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || defined(CONFIG_MPC8306) /* SCCR bits - MPC8315/MPC8308 specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30