On 09/07/2016 03:33 PM, Chin Liang See wrote:
On Tue, 2016-09-06 at 14:15 +0200, Marek Vasut wrote:
On 09/06/2016 11:18 AM, Chin Liang See wrote:
On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
On 08/22/2016 05:02 PM, Chin Liang See wrote:
Add support for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See clsee@altera.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Ley Foon Tan lftan@altera.com
arch/arm/Kconfig | 7 +- arch/arm/mach-socfpga/Kconfig | 10 +++ configs/socfpga_stratix10_defconfig | 14 ++++ include/configs/socfpga_stratix10_socdk.h | 135 ++++++++++++++++++++++++++++++ 4 files changed, 163 insertions(+), 3 deletions(-) create mode 100755 configs/socfpga_stratix10_defconfig create mode 100644 include/configs/socfpga_stratix10_socdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c..c8e8767 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA bool "Altera SOCFPGA family"
select CPU_V7select SUPPORT_SPL
select CPU_V7 if !TARGET_SOCFPGA_STRATIX10select ARM64 if TARGET_SOCFPGA_STRATIX10select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10 select OF_CONTROL
select SPL_OF_CONTROL
select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10Why is the SPL disabled ?
We will be having SPL for Stratix 10. It will added in later days as SPL main function is for DDR setup. This is not needed for SOC Virtual Platform now.
Please do things right from the start, add the SPL and skip the DRAM init if it's not needed.
That is my next to do list as I am enabling the Stratix 10 by phases. In this case, I shall repost this series once getting SPL available.
That's fine. When do you see that happening ?