On 15/09/2023 18:01, Jerome Brunet wrote:
Amlogic MMC on the GX (and later) SoCs has been problematic for years, especially with u-boot.
Linux has been fairly stable for a few years. It is using a fixed phase setting with Core = 180, Tx = 0 and Rx = 0 (the latter cannot be set starting from the v3 MMC IPs)
Still the results were not good with those settings with u-boot, on some sm1 based platforms. U-boot then started using a 270 core phase for sm1 only. This worked for most sm1 platforms but problems persist on others.
The proposal with this patchset is to use 270 for the ID phase, 180 otherwise. This works well on the platforms I have tested (Libretech's boards and VIM3L)
It would be great if others could test this and report whether this work for them or not.
If the results are good, this might be ported to Linux as well (... but the situation is less critical there)
Jerome Brunet (2): mmc: meson-gx: clean up and align on Linux settings mmc: meson-gx: set 270 core phase during the identification
drivers/mmc/meson_gx_mmc.c | 50 ++++++++++++++++++-------------------- drivers/mmc/meson_gx_mmc.h | 9 +++++-- 2 files changed, 31 insertions(+), 28 deletions(-)
I got a regression with this patchset on the BPI M5 (SM1) SDCard, u-boot pytest results: - https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/jobs/5603936884 - full HTML log: https://amlogic-foss.gitlab.io/-/amlogic-u-boot-autotest/-/jobs/5603936884/a... Same device but without the patch: - https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/jobs/5601899556 - full HTML log: https://amlogic-foss.gitlab.io/-/amlogic-u-boot-autotest/-/jobs/5601899556/a... Same branch but on A311D gives expected results: - https://gitlab.com/amlogic-foss/amlogic-u-boot-autotest/-/jobs/5603932746 - full HTML log: https://amlogic-foss.gitlab.io/-/amlogic-u-boot-autotest/-/jobs/5603932746/a...
eMMC devices gets 26MHz speed instead of 52MHz, and SD reads and writes gives random errors:
=> mmc info Device: mmc@ffe07000 Manufacturer ID: 15 OEM: 0 Name: AJTD4R Bus Speed: 26000000 Mode: MMC High Speed (26MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 4 MiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 14.6 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected
=> mmc dev 0 ** fs_devread read error - block switch to partitions #0, OK mmc0 is current device => mmc read 0x00200000 0 1000 MMC read: dev # 0, block # 0, count 4096 ... 0 blocks read: ERROR => mmc write 0x00200000 200000 3e8 MMC write: dev # 0, block # 2097152, count 1000 ... 0 blocks written: ERROR
I ran the test twice to be sure.
Neil