Re: [U-Boot] [PATCH 4/6] sbc8548: correct local bus SDRAM size from 64M to 128M

Dear Paul Gortmaker,

In message 5ad17f25a126b25be24467d1712d30a775a5b494.1253492532.git.paul.gortmaker@windriver.com you wrote:

The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM.

Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com

...

• * TLB 6:	64M	Cacheable, non-guarded
  

• * 0xf4000000	64M	LBC SDRAM Second half
  

• */
  

• SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,

Line too long.

Best regards,

Wolfgang Denk