On 11/24/2016 08:10 PM, Michael Kurz wrote:
This patch adds support for the QSPI IP found in stm32f7 devices.
Signed-off-by: Michael Kurz michi.kurz@gmail.com
This currently hard disables any multi i/o in the device tree, as it is impossible to get this working without interpreting the commands of the spi-flash framework in the xfer function and setting the used i/o lines accordingly. As i understand a spi-nor framework is currently in the making which addresses these problems. Should i base this driver on the new framework or is it ok in the current form and should later be ported to the new one?
Changes in v3:
- Moved qspi rcc bits into rcc header
- Drop 'add missing flag to micron/stm N25Q128 flash chips' patch
Changes in v2:
- Replaced bit shifts and masks with BIT() and GENMASK() macro
arch/arm/dts/stm32f746-disco.dts | 4 +- arch/arm/include/asm/arch-stm32f7/rcc.h | 1 + arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 6 +- arch/arm/mach-stm32/stm32f7/clock.c | 3 + board/st/stm32f746-disco/stm32f746-disco.c | 60 +++ configs/stm32f746-disco_defconfig | 7 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/stm32_qspi.c | 628 +++++++++++++++++++++++ 9 files changed, 714 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/stm32_qspi.c
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 7b652f0..b58889a 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -146,8 +146,8 @@ #size-cells = <1>; compatible = "micron,n25q128a13", "spi-flash"; spi-max-frequency = <108000000>;
spi-tx-bus-width = <4>;spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;spi-rx-bus-width = <1>;
This shouldn't be part of this patch , right ?
memory-map = <0x90000000 0x1000000>; reg = <0>;};
[...]
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c new file mode 100644 index 0000000..123a1f3 --- /dev/null +++ b/drivers/spi/stm32_qspi.c @@ -0,0 +1,628 @@ +/*
- (C) Copyright 2016
- Michael Kurz, michi.kurz@gmail.com
- STM32 QSPI driver
Is this compatible with the cadence qspi or not ?