Hi Bin,
On Thu, 8 Apr 2021 at 14:23, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, Apr 7, 2021 at 12:32 PM Simon Glass sjg@chromium.org wrote:
At present this driver relies on coreboot to provide information about the console UART. However if coreboot is not compiled with the UART enabled, the information is left out. This configuration is quite common, e.g. with shipping x86-based Chrome OS Chromebooks.
Add a way to determine the UART settings in this case, using a hard-coded list of PCI IDs.
Signed-off-by: Simon Glass sjg@chromium.org
drivers/serial/serial_coreboot.c | 68 ++++++++++++++++++++++++++++---- include/pci_ids.h | 1 + 2 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c index de09c8681f5..4b4619432d8 100644 --- a/drivers/serial/serial_coreboot.c +++ b/drivers/serial/serial_coreboot.c @@ -11,19 +11,71 @@ #include <serial.h> #include <asm/cb_sysinfo.h>
+static const struct pci_device_id ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2) },{},+};
+/*
- Coreboot only sets up the UART if it uses it and doesn't bother to put the
- details in sysinfo if it doesn't. Try to guess in that case, using devices
- we know about
- @plat: Platform data to fill in
- @return 0 if found, -ve if no UART was found
- */
+static int guess_uart(struct ns16550_plat *plat)
This is really not a guess, but use a pre-configured platform data. Also this only work for Apollo Lake board, and will break other boards if they don't have cbinfo available.
Which bit of it breaks other boards?
Why not just simply put a serial node in the device tree and we are all done?
See my other email...I am trying to make this boot on any board that coreboot supports.
[..]
Regards, Simon