Hi Niklaus,
On Friday 02 March 2007 16:51, Niklaus Giger wrote:
Our HW engineers discovered that the U-Boot commands icache/dcache do not work on PPC440x boards (at least yosemite and sequoia).
Correct. On all 44x U-Boot platform cache in SDRAM is disabled right now. The main reason for this is the the 4xx EMAC driver needs it's buffer descriptors in uncached memory, or it must be changed to work with cached buffers too (invalidate & flush...).
In my opinion icache/dcache work only on PPC40x processors where one can alter the ICCR/DCCR registert. For the PPC440x register one should tinker with the corresponding SA_I bit in the TLB.
Right.
Has somebody already solved this problem and would be willing to share his patch?
From my point of view it doesn't make sense to support the icache/dcache commands for the 44x platforms. No real gain here. What makes real sense is to enable cache support in SDRAM. I have started working on an 440 port with caches enabled in SDRAM but other, more important stuff came in-between.
As mentioned above the main problem is the EMAC driver. It has either to be changed to support cache handling (invalidating/flushing) of the buffer descriptors. Or we must setup one small area in the SDRAM that is uncached and the driver uses this memory area for the buffer descriptors.
If not I am willing to work on patch along the following lines:
a) add some C-callable routines to cpu/ppc4xx/start.S to use the TLB Search Instruction and b) to modify/setup a TLB from C c) add in cpu/ppc4xx/cpu.c d/icache_dis/enable procedure Any objections/comments?
As mentioned above, I see no real gain here. If you really want to start on this issue, then please rework the EMAC driver as mentioned above and we can enable the caches in SDRAM. This would really bring a performance boost to the 44x platforms (image uncompressing, ECC generation, FPGA programming...).
But I have to admit the EMAC driver is total mess of #ifdef's (again)! :-(
Best regards, Stefan
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