Re: [U-Boot] [PATCH 1/7] pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family

Am 06.01.19 um 18:23 schrieb Horatiu Vultur:

The Jaguar2 SOC family has 63 gpio pins therefore I extented mscc-common to support new number of pins.

Signed-off-by: Horatiu Vultur horatiu.vultur@microchip.com

MAINTAINERS | 1 + drivers/pinctrl/mscc/Kconfig | 9 ++ drivers/pinctrl/mscc/Makefile | 1 + drivers/pinctrl/mscc/mscc-common.c | 122 ++++++++++++--- drivers/pinctrl/mscc/pinctrl-jr2.c | 302 +++++++++++++++++++++++++++++++++++++ 5 files changed, 411 insertions(+), 24 deletions(-) create mode 100644 drivers/pinctrl/mscc/pinctrl-jr2.c

diff --git a/MAINTAINERS b/MAINTAINERS index 494962e..495d3e5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -525,6 +525,7 @@ F: board/mscc/ F: configs/mscc* F: drivers/gpio/mscc_sgpio.c F: include/configs/vcoreiii.h +F: drivers/pinctrl/mscc/

MIPS JZ4780 M: Ezequiel Garcia ezequiel@collabora.com diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig index cfc6c06..d07ea1b 100644 --- a/drivers/pinctrl/mscc/Kconfig +++ b/drivers/pinctrl/mscc/Kconfig @@ -20,3 +20,12 @@ config PINCTRL_MSCC_LUTON help Support pin multiplexing and pin configuration control on Microsemi luton SoCs.

+config PINCTRL_MSCC_JR2

• depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
• select PINCTRL_MSCC
• default y
• bool "Microsemi jr2 family pin control driver"
• help

•    Support pin multiplexing and pin configuration control on
  

•    Microsemi jr2 SoCs.
  

diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile index 6910671..8038d54 100644 --- a/drivers/pinctrl/mscc/Makefile +++ b/drivers/pinctrl/mscc/Makefile @@ -3,3 +3,4 @@ obj-y += mscc-common.o obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o +obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c index d74b8a6..5cb7d35 100644 --- a/drivers/pinctrl/mscc/mscc-common.c +++ b/drivers/pinctrl/mscc/mscc-common.c @@ -22,6 +22,18 @@ #include <linux/io.h> #include "mscc-common.h"

+#if defined(CONFIG_SOC_JR2) +#define MSCC_GPIO_OUT_SET 0x00 +#define MSCC_GPIO_OUT_CLR 0x08 +#define MSCC_GPIO_OUT 0x10 +#define MSCC_GPIO_IN 0x18 +#define MSCC_GPIO_OE 0x20 +#define MSCC_GPIO_INTR 0x28 +#define MSCC_GPIO_INTR_ENA 0x30 +#define MSCC_GPIO_INTR_IDENT 0x38 +#define MSCC_GPIO_ALT0 0x40 +#define MSCC_GPIO_ALT1 0x48 +#else #define MSCC_GPIO_OUT_SET 0x0 #define MSCC_GPIO_OUT_CLR 0x4 #define MSCC_GPIO_OUT 0x8 @@ -31,7 +43,39 @@ #define MSCC_GPIO_INTR_ENA 0x18 #define MSCC_GPIO_INTR_IDENT 0x1c #define MSCC_GPIO_ALT0 0x20 -#define MSCC_GPIO_ALT1 0x24 +#endif

+static void mscc_writel(unsigned int offset, void *addr) +{

• if (offset < 32)

• writel(BIT(offset), addr);
  

• else

• writel(BIT(offset % 32), addr + 4);
  

+}

+static unsigned int mscc_readl(unsigned int offset, void *addr) +{

• if (offset < 32)

• return readl(addr);
  

• else

• return readl(addr + 4);
  

+}

+static void mscc_setbits(unsigned int offset, void *addr) +{

• if (offset < 32)

• writel(readl(addr) | BIT(offset), addr);
  

• else

• writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
  

+}

+static void mscc_clrbits(unsigned int offset, void *addr) +{

• if (offset < 32)

• writel(readl(addr) & ~BIT(offset), addr);
  

• else

• writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
  

+}

static int mscc_get_functions_count(struct udevice *dev) { @@ -67,7 +111,7 @@ static int mscc_pinmux_set_mux(struct udevice *dev, { struct mscc_pinctrl *info = dev_get_priv(dev); struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;

• int f;

• int f, offset, regoff;

  f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins); if (f < 0)

@@ -79,15 +123,25 @@ static int mscc_pinmux_set_mux(struct udevice *dev, * This is racy because both registers can't be updated at the same time * but it doesn't matter much for now. */

• offset = pin->pin;
• regoff = MSCC_GPIO_ALT0;
• /* Handle GPIOs 32-63 */

+#if defined(MSCC_GPIO_ALT1)

• if (offset >= 32) {

• offset = offset % 32;
  

• regoff = MSCC_GPIO_ALT1;
  

• }

+#endif

• if (f & BIT(0))

• setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
  

• mscc_setbits(offset, info->regs + regoff);
  

  else

• clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
  

• mscc_clrbits(offset, info->regs + regoff);
  
  

  if (f & BIT(1))

• setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
  

• mscc_setbits(offset, info->regs + regoff + 4);
  

  else

• clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
  

• mscc_clrbits(offset, info->regs + regoff + 4);
  
  

  return 0;

}

this design of putting SoC specific code in common code is a little bit strange. If the JR2 behaves differently then Ocelot/Luton, then you should annotate the common function as __weak and reimplement this function in the JR2 source file.

@@ -120,8 +174,8 @@ static int mscc_create_group_func_map(struct udevice *dev, }

info->func[f].ngroups = npins;

• info->func[f].groups = devm_kzalloc(dev, npins *
  

• 				    sizeof(char *), GFP_KERNEL);
  

• info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
  

• 				    GFP_KERNEL);
  

  if (!info->func[f].groups) return -ENOMEM;

@@ -132,7 +186,8 @@ static int mscc_create_group_func_map(struct udevice *dev, return 0; }

-static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info) +static int mscc_pinctrl_register(struct udevice *dev,

• 		 struct mscc_pinctrl *info)
  

{ int ret;

@@ -150,38 +205,44 @@ static int mscc_gpio_get(struct udevice *dev, unsigned int offset) struct mscc_pinctrl *info = dev_get_priv(dev->parent); unsigned int val;

• val = readl(info->regs + MSCC_GPIO_IN);

• if (mscc_readl(offset, info->regs + MSCC_GPIO_OE) & BIT(offset % 32))

• val = mscc_readl(offset, info->regs + MSCC_GPIO_OUT);
  

• else

• val = mscc_readl(offset, info->regs + MSCC_GPIO_IN);
  
  

• return !!(val & BIT(offset));

• return !!(val & BIT(offset % 32));

}

-static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value) +static int mscc_gpio_set(struct udevice *dev, unsigned int offset,

• 	 int value)
  

{ struct mscc_pinctrl *info = dev_get_priv(dev->parent);

if (value)

• writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
  

• mscc_writel(offset, info->regs + MSCC_GPIO_OUT_SET);
  

  else

• writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
  

• mscc_writel(offset, info->regs + MSCC_GPIO_OUT_CLR);
  
  

  return 0;

}

-static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset) +static int mscc_gpio_get_direction(struct udevice *dev,

• 		   unsigned int offset)
  

{ struct mscc_pinctrl *info = dev_get_priv(dev->parent); unsigned int val;

• val = readl(info->regs + MSCC_GPIO_OE);

• val = mscc_readl(offset, info->regs + MSCC_GPIO_OE);

• return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;

• return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;

}

-static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset) +static int mscc_gpio_direction_input(struct udevice *dev,

• 		     unsigned int offset)
  

{ struct mscc_pinctrl *info = dev_get_priv(dev->parent);

• clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));

• mscc_clrbits(offset, info->regs + MSCC_GPIO_OE);

  return 0;

} @@ -191,7 +252,7 @@ static int mscc_gpio_direction_output(struct udevice *dev, { struct mscc_pinctrl *info = dev_get_priv(dev->parent);

• setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));

• mscc_setbits(offset, info->regs + MSCC_GPIO_OE);

  return mscc_gpio_set(dev, offset, value);

} @@ -215,15 +276,20 @@ const struct pinctrl_ops mscc_pinctrl_ops = {

int mscc_pinctrl_probe(struct udevice *dev, int num_func, const struct mscc_pin_data *mscc_pins, int num_pins,

•        char *const *function_names)
  

•        char * const*function_names)
  

{ struct mscc_pinctrl *priv = dev_get_priv(dev);

• struct uclass_driver *drv;
• fdt_addr_t addr;
• fdt_size_t size; int ret;

• priv->regs = dev_remap_addr(dev);
• if (!priv->regs)

• addr = devfdt_get_addr_size_index(dev, 0, &size);

• if (addr == FDT_ADDR_T_NONE) return -EINVAL;

• priv->regs = ioremap(addr, size);

do not replace the new DM API with the old one

priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func), GFP_KERNEL); priv->num_func = num_func; @@ -231,6 +297,14 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func, priv->num_pins = num_pins; priv->function_names = function_names; ret = mscc_pinctrl_register(dev, priv);

• if (ret)

• return ret;
  
  

• return ret;

• drv = lists_uclass_lookup(UCLASS_GPIO);
• if (!drv) {

• puts("Cannot find GPIO driver\n");
  

• return -ENOENT;
  

• }

what is that for, just error checking?

• return 0;

} diff --git a/drivers/pinctrl/mscc/pinctrl-jr2.c b/drivers/pinctrl/mscc/pinctrl-jr2.c new file mode 100644 index 0000000..fa48b37 --- /dev/null +++ b/drivers/pinctrl/mscc/pinctrl-jr2.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/*

• • Microsemi SoCs pinctrl driver
• • Author: horatiu.vultur@microchip.com
• • License: Dual MIT/GPL
• • Copyright (c) 2018 Microsemi Corporation
• */

+#include <common.h> +#include <config.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <errno.h> +#include <fdtdec.h> +#include <linux/io.h> +#include <asm/gpio.h> +#include <asm/system.h> +#include "mscc-common.h"

+enum {

• FUNC_NONE,
• FUNC_GPIO,
• FUNC_IRQ0_IN,
• FUNC_IRQ0_OUT,
• FUNC_IRQ1_IN,
• FUNC_IRQ1_OUT,
• FUNC_MIIM1,
• FUNC_MIIM2,
• FUNC_PCI_WAKE,
• FUNC_PTP0,
• FUNC_PTP1,
• FUNC_PTP2,
• FUNC_PTP3,
• FUNC_PWM,
• FUNC_RECO_CLK0,
• FUNC_RECO_CLK1,
• FUNC_SFP0,
• FUNC_SFP1,
• FUNC_SFP2,
• FUNC_SFP3,
• FUNC_SFP4,
• FUNC_SFP5,
• FUNC_SFP6,
• FUNC_SFP7,
• FUNC_SFP8,
• FUNC_SFP9,
• FUNC_SFP10,
• FUNC_SFP11,
• FUNC_SFP12,
• FUNC_SFP13,
• FUNC_SFP14,
• FUNC_SFP15,
• FUNC_SIO,
• FUNC_SIO1,
• FUNC_SIO2,
• FUNC_SI,
• FUNC_TACHO,
• FUNC_TWI,
• FUNC_TWI2,
• FUNC_TWI_SCL_M,
• FUNC_UART,
• FUNC_UART2,
• FUNC_MAX

+};

+char *jr2_function_names[] = {

• [FUNC_NONE] = "none",
• [FUNC_GPIO] = "gpio",
• [FUNC_IRQ0_IN] = "irq0_in",
• [FUNC_IRQ0_OUT] = "irq0_out",
• [FUNC_IRQ1_IN] = "irq1_in",
• [FUNC_IRQ1_OUT] = "irq1_out",
• [FUNC_MIIM1] = "miim1",
• [FUNC_MIIM2] = "miim2",
• [FUNC_PCI_WAKE] = "pci_wake",
• [FUNC_PTP0] = "ptp0",
• [FUNC_PTP1] = "ptp1",
• [FUNC_PTP2] = "ptp2",
• [FUNC_PTP3] = "ptp3",
• [FUNC_PWM] = "pwm",
• [FUNC_RECO_CLK0] = "reco_clk0",
• [FUNC_RECO_CLK1] = "reco_clk1",
• [FUNC_SFP0] = "sfp0",
• [FUNC_SFP1] = "sfp1",
• [FUNC_SFP2] = "sfp2",
• [FUNC_SFP3] = "sfp3",
• [FUNC_SFP4] = "sfp4",
• [FUNC_SFP5] = "sfp5",
• [FUNC_SFP6] = "sfp6",
• [FUNC_SFP7] = "sfp7",
• [FUNC_SFP8] = "sfp8",
• [FUNC_SFP9] = "sfp9",
• [FUNC_SFP10] = "sfp10",
• [FUNC_SFP11] = "sfp11",
• [FUNC_SFP12] = "sfp12",
• [FUNC_SFP13] = "sfp13",
• [FUNC_SFP14] = "sfp14",
• [FUNC_SFP15] = "sfp15",
• [FUNC_SIO] = "sio",
• [FUNC_SIO1] = "sio1",
• [FUNC_SIO2] = "sio2",
• [FUNC_SI] = "si",
• [FUNC_TACHO] = "tacho",
• [FUNC_TWI] = "twi",
• [FUNC_TWI2] = "twi2",
• [FUNC_TWI_SCL_M] = "twi_scl_m",
• [FUNC_UART] = "uart",
• [FUNC_UART2] = "uart2",

+};

+MSCC_P(0, SIO, NONE, NONE); +MSCC_P(1, SIO, NONE, NONE); +MSCC_P(2, SIO, NONE, NONE); +MSCC_P(3, SIO, NONE, NONE); +MSCC_P(4, SIO1, NONE, NONE); +MSCC_P(5, SIO1, NONE, NONE); +MSCC_P(6, IRQ0_IN, IRQ0_OUT, NONE); +MSCC_P(7, IRQ1_IN, IRQ1_OUT, NONE); +MSCC_P(8, PTP0, NONE, NONE); +MSCC_P(9, PTP1, NONE, NONE); +MSCC_P(10, UART, NONE, NONE); +MSCC_P(11, UART, NONE, NONE); +MSCC_P(12, SIO1, NONE, NONE); +MSCC_P(13, SIO1, NONE, NONE); +MSCC_P(14, TWI, TWI_SCL_M, NONE); +MSCC_P(15, TWI, NONE, NONE); +MSCC_P(16, SI, TWI_SCL_M, NONE); +MSCC_P(17, SI, TWI_SCL_M, NONE); +MSCC_P(18, SI, TWI_SCL_M, NONE); +MSCC_P(19, PCI_WAKE, NONE, NONE); +MSCC_P(20, IRQ0_OUT, TWI_SCL_M, NONE); +MSCC_P(21, IRQ1_OUT, TWI_SCL_M, NONE); +MSCC_P(22, TACHO, NONE, NONE); +MSCC_P(23, PWM, NONE, NONE); +MSCC_P(24, UART2, NONE, NONE); +MSCC_P(25, UART2, SI, NONE); +MSCC_P(26, PTP2, SI, NONE); +MSCC_P(27, PTP3, SI, NONE); +MSCC_P(28, TWI2, SI, NONE); +MSCC_P(29, TWI, SI, NONE); +MSCC_P(30, SIO2, SI, NONE); +MSCC_P(31, SIO2, SI, NONE); +MSCC_P(32, SIO2, SI, NONE); +MSCC_P(33, SIO2, SI, NONE); +MSCC_P(34, NONE, TWI_SCL_M, NONE); +MSCC_P(35, NONE, TWI_SCL_M, NONE); +MSCC_P(36, NONE, TWI_SCL_M, NONE); +MSCC_P(37, NONE, TWI_SCL_M, NONE); +MSCC_P(38, NONE, TWI_SCL_M, NONE); +MSCC_P(39, NONE, TWI_SCL_M, NONE); +MSCC_P(40, NONE, TWI_SCL_M, NONE); +MSCC_P(41, NONE, TWI_SCL_M, NONE); +MSCC_P(42, NONE, TWI_SCL_M, NONE); +MSCC_P(43, NONE, TWI_SCL_M, NONE); +MSCC_P(44, NONE, SFP8, NONE); +MSCC_P(45, NONE, SFP9, NONE); +MSCC_P(46, NONE, SFP10, NONE); +MSCC_P(47, NONE, SFP11, NONE); +MSCC_P(48, SFP0, NONE, NONE); +MSCC_P(49, SFP1, SI, NONE); +MSCC_P(50, SFP2, SI, NONE); +MSCC_P(51, SFP3, SI, NONE); +MSCC_P(52, SFP4, NONE, NONE); +MSCC_P(53, SFP5, NONE, NONE); +MSCC_P(54, SFP6, NONE, NONE); +MSCC_P(55, SFP7, NONE, NONE); +MSCC_P(56, MIIM1, SFP12, NONE); +MSCC_P(57, MIIM1, SFP13, NONE); +MSCC_P(58, MIIM2, SFP14, NONE); +MSCC_P(59, MIIM2, SFP15, NONE); +MSCC_P(60, NONE, NONE, NONE); +MSCC_P(61, NONE, NONE, NONE); +MSCC_P(62, NONE, NONE, NONE); +MSCC_P(63, NONE, NONE, NONE);

+#define JR2_PIN(n) { \

• .name = "GPIO_"#n, \
• .drv_data = &mscc_pin_##n \

+}

+const struct mscc_pin_data jr2_pins[] = {

• JR2_PIN(0),
• JR2_PIN(1),
• JR2_PIN(2),
• JR2_PIN(3),
• JR2_PIN(4),
• JR2_PIN(5),
• JR2_PIN(6),
• JR2_PIN(7),
• JR2_PIN(8),
• JR2_PIN(9),
• JR2_PIN(10),
• JR2_PIN(11),
• JR2_PIN(12),
• JR2_PIN(13),
• JR2_PIN(14),
• JR2_PIN(15),
• JR2_PIN(16),
• JR2_PIN(17),
• JR2_PIN(18),
• JR2_PIN(19),
• JR2_PIN(20),
• JR2_PIN(21),
• JR2_PIN(22),
• JR2_PIN(23),
• JR2_PIN(24),
• JR2_PIN(25),
• JR2_PIN(26),
• JR2_PIN(27),
• JR2_PIN(28),
• JR2_PIN(29),
• JR2_PIN(30),
• JR2_PIN(31),
• JR2_PIN(32),
• JR2_PIN(33),
• JR2_PIN(34),
• JR2_PIN(35),
• JR2_PIN(36),
• JR2_PIN(37),
• JR2_PIN(38),
• JR2_PIN(39),
• JR2_PIN(40),
• JR2_PIN(41),
• JR2_PIN(42),
• JR2_PIN(43),
• JR2_PIN(44),
• JR2_PIN(45),
• JR2_PIN(46),
• JR2_PIN(47),
• JR2_PIN(48),
• JR2_PIN(49),
• JR2_PIN(50),
• JR2_PIN(51),
• JR2_PIN(52),
• JR2_PIN(53),
• JR2_PIN(54),
• JR2_PIN(55),
• JR2_PIN(56),
• JR2_PIN(57),
• JR2_PIN(58),
• JR2_PIN(59),
• JR2_PIN(60),
• JR2_PIN(61),
• JR2_PIN(62),
• JR2_PIN(63),

+};

+static int jr2_gpio_probe(struct udevice *dev) +{

• struct gpio_dev_priv *uc_priv;
• uc_priv = dev_get_uclass_priv(dev);
• uc_priv->bank_name = "jr2-gpio";
• uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
• return 0;

+}

+static struct driver jr2_gpio_driver = {

• .name = "jr2-gpio",
• .id = UCLASS_GPIO,
• .probe = jr2_gpio_probe,
• .ops = &mscc_gpio_ops,

+};

+int jr2_pinctrl_probe(struct udevice *dev) +{

• int ret;
• ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,

• 		 ARRAY_SIZE(jr2_pins),
  

• 		 jr2_function_names);
  

• if (ret)

• return ret;
  

• ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,

• 	  dev_of_offset(dev), NULL);
  

• if (ret)

• return ret;
  

• return 0;

+}

+static const struct udevice_id jr2_pinctrl_of_match[] = {

• { .compatible = "mscc,jr2-pinctrl" },
• {},

+};

+U_BOOT_DRIVER(jr2_pinctrl) = {

• .name = "jr2-pinctrl",
• .id = UCLASS_PINCTRL,
• .of_match = of_match_ptr(jr2_pinctrl_of_match),
• .probe = jr2_pinctrl_probe,
• .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
• .ops = &mscc_pinctrl_ops,

+};