From: Holger Brunck holger.brunck@keymile.com
To be prepared for mgcoge3ne which has a different SDRAM on board. The config was moved from generic code to board specific header.
Signed-off-by: Holger Brunck holger.brunck@keymile.com Acked-by: Heiko Schocher hs@denx.de cc: Wolfgang Denk wd@denx.de cc: Detlev Zundel dzu@denx.de cc: Valentin Longchamp valentin.longchamp@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- include/configs/km82xx-common.h | 26 -------------------------- include/configs/mgcoge.h | 26 ++++++++++++++++++++++++++ include/configs/mgcoge2ne.h | 23 +++++++++++++++++++++++ 3 files changed, 49 insertions(+), 26 deletions(-)
diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h index 345212c..da551c9 100644 --- a/include/configs/km82xx-common.h +++ b/include/configs/km82xx-common.h @@ -243,13 +243,6 @@ ORxG_SCY_5_CLK |\ ORxG_TRLX)
- -/* - * Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - #define CONFIG_SYS_MPTPR 0x1800
/* @@ -268,25 +261,6 @@ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
/* - * SDRAM initialization values - */ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values */ #define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 3d2ee24..aed1526 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -58,6 +58,32 @@ CONFIG_SYS_FLASH_BASE_2 } #define MTDIDS_DEFAULT "nor3=app"
+/* + * Bank 1 - 60x bus SDRAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +/* SDRAM initialization values +*/ + +#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ + ORxS_SDAM_MSK) |\ + ORxS_BPD_8 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + + /* include further common stuff for all keymile 82xx boards */ #include "km82xx-common.h"
diff --git a/include/configs/mgcoge2ne.h b/include/configs/mgcoge2ne.h index 287b717..2b09b42 100644 --- a/include/configs/mgcoge2ne.h +++ b/include/configs/mgcoge2ne.h @@ -58,6 +58,29 @@
#define MTDIDS_DEFAULT "nor2=app"
+/* + * Bank 1 - 60x bus SDRAM + * mgcoge2ne has 128M RAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ + ORxS_SDAM_MSK) |\ + ORxS_BPD_8 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) + +#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_5_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) + /* include further common stuff for all keymile 82xx boards */ #include "km82xx-common.h"