Add edminiv2 board support for mv_egiga. Add edminiv2 config to enable mv_egiga.
Signed-off-by: Albert Aribaud albert.aribaud@free.fr --- board/LaCie/edminiv2/edminiv2.c | 36 ++++++++++++++++++++++++++++++++++ board/LaCie/edminiv2/edminiv2.h | 41 +++++++++++++++++++++++++++++++++++++++ include/configs/edminiv2.h | 19 ++++++++++++++--- 3 files changed, 92 insertions(+), 4 deletions(-) create mode 100644 board/LaCie/edminiv2/edminiv2.h
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 54c0ffe..bb388ed 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -27,6 +27,7 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/orion5x.h> +#include "edminiv2.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -90,3 +91,38 @@ int board_init(void)
return 0; } + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h new file mode 100644 index 0000000..88e62b2 --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __EDMINIV2_BASE_H +#define __EDMINIV2_BASE_H + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __EDMINIV2_BASE_H */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index c3d95a0..055931c 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -131,12 +131,23 @@ * Commands configuration - using default command set for now */ #include <config_cmd_default.h> + /* - * Disabling some default commands for staggered bring-up + * Network */ -#undef CONFIG_CMD_BOOTD /* no bootd since no net */ -#undef CONFIG_CMD_NET /* no net since no eth */ -#undef CONFIG_CMD_NFS /* no NFS since no net */ + +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE /* Enable Marvell GbE Driver */ +#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ +#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ +#define CONFIG_PHY_BASE_ADR 0x8 +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#endif
/* * Environment variables configurations