9 Dec
2024
9 Dec
'24
1:12 p.m.
Hi Miquel,
On Thu, Dec 5, 2024 at 10:54 AM Miquel Raynal miquel.raynal@bootlin.com wrote:
In order to display a boot picture or an error message, the i.MX8MP display pipeline must be enabled. The SoC has support for various interfaces (LVDS, HDMI, DSI). The one supported in this series is the standard 4-lane LVDS output. The minimal setup is thus composed of:
- An LCD InterFace (LCDIF) with an AXI/APB interface, generating a pixel stream
- One LVDS Display Bridge (LDB), also named pixel mapper, which receives the pixel stream and route it to one or two (possibly combined) LVDS displays.
- All necessary clocks and power controls coming from the MEDIAMIX control block.
There are errors in CI when this series is applied.
Please take a look at the sandbox test failures:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23735
Also, please make sure that v3 passes Azure CI tests.