RE: [v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz

-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz

Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex.

This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz.

Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com

---

arch/arm/mach-socfpga/clock_manager.c | 5 +-- .../include/mach/system_manager_soc64.h | 16 ++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 40 +++++++++++++++++++--- include/configs/socfpga_soc64_common.h | 1 + 4 files changed, 55 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach- socfpga/clock_manager.c index be426a5cfb..2783b9d18d 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -67,8 +67,9 @@ int set_cpu_clk_info(void) #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) unsigned int cm_get_qspi_controller_clk_hz(void) {

• return readl(socfpga_get_sysmgr_addr() +

•      SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
  

• return (readl(socfpga_get_sysmgr_addr() +

•      SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
  

•      SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) *
  

CLOCK_1K; } #endif

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 1eb8e7a904..fc4e17821b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/*

• • Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for

+SOC 64-bit

• • storing qspi ref clock (kHz)
• */

#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400

+/*

• • Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
• • Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for

+SOC 64-bit

• • storing qspi ref clock (kHz)
• */

+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28

#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC

#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach- socfpga/mailbox_s10.c index 7dcdae8136..2a13fbb506 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -356,6 +356,38 @@ int mbox_qspi_close(void) 0, NULL, 0, 0, NULL); }

+int mbox_qspi_set_controller_clk_hz(int clk_hz) {

This function nothing related to mailbox. Change to other name and move the function to the place read qspi clock. Then can remove define CLOCK_1K from socfpga_soc64_common.h.

• u32 reg;
• u32 clk_khz;
• /* We are getting QSPI ref clock and set into sysmgr boot register */
• /*

• * Only clock freq in kHz degree is accepted due to limited bits[27:0]
  

• * is reserved for storing the QSPI clock freq into boot scratch cold0
  

• * register
  

• */
  

• if (clk_hz < CLOCK_1K)

• return -EINVAL;
  

• clk_khz = clk_hz / CLOCK_1K;
• printf("QSPI: Reference clock at %d kHz\n", clk_khz);
• /*

• * DDR retention bit, SHA comparison bit and reset type bits sharing
  

the

• * same scratch register in N5X, ensure the content inside register is
  

• * not overwritten by QSPI ref clock (kHz)
  

• */
  

Comment doesn't need to mention about DDR retention. This is for N5X only. This just to clear the intended bits only.

• reg = (readl(socfpga_get_sysmgr_addr() +

•      SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
  

•      ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
  

• writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) |

reg,

•       socfpga_get_sysmgr_addr() +
  

SYSMGR_SOC64_BOOT_SCRATCH_COLD0);

• return 0;

+}

int mbox_qspi_open(void) { int ret; @@ -384,10 +416,10 @@ int mbox_qspi_open(void) if (ret) goto error;

• /* We are getting QSPI ref clock and set into sysmgr boot register */
• printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
• writel(resp_buf[0],

•       socfpga_get_sysmgr_addr() +
  

SYSMGR_SOC64_BOOT_SCRATCH_COLD0);

• /* Store QSPI controller ref clock frequency*/

• ret = mbox_qspi_set_controller_clk_hz(resp_buf[0]);

• if (ret)

• goto error;
  
  

  return 0;

diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 5afdb10454..6a157298ca 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -73,6 +73,7 @@

#ifndef __ASSEMBLY__ unsigned int cm_get_qspi_controller_clk_hz(void); +#define CLOCK_1K 1000 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif

-- 2.13.0