Grant,
On Wednesday 21 May 2008, Grant Erickson wrote:
This patch (Part 2 of 2):
Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code.
Enables MCSR visibility on the 405EX(r).
Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value.
With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it.
Thanks a lot for all this work. Please find some comments below.
Signed-off-by: Grant Erickson gerickson@nuovations.com
board/amcc/kilauea/init.S | 229 +++++++++++++++++--------------- board/amcc/kilauea/memory.c | 5 + board/amcc/makalu/init.S | 125 +----------------- board/amcc/makalu/memory.c | 118 +---------------- include/configs/kilauea.h | 110 ++++++++++++++-- include/configs/makalu.h | 114 ++++++++++++++-- 6 files
diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S index 053fe19..bf47d6b 100644 --- a/board/amcc/kilauea/init.S +++ b/board/amcc/kilauea/init.S @@ -1,8 +1,11 @@ /*
- Copyright (c) 2008 Nuovation System Designs, LLC
- Grant Erickson gerickson@nuovations.com
- (C) Copyright 2007-2008
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- Based on code provided from UDTech and AMCC
- Originally based on code provided from UDTech and AMCC
- See file CREDITS for list of people who contributed to this
- project.
@@ -29,126 +32,136 @@ #include <ppc_asm.tmpl> #include <ppc_defs.h>
-#define mtsdram_as(reg, value) \
- addi r4,0,reg ; \
- mtdcr memcfga,r4 ; \
- addis r4,0,value@h ; \
- ori r4,r4,value@l ; \
- mtdcr memcfgd,r4 ;
+#define mtsdram_as(reg, value) \
- addi r4,0,reg ; \
- mtdcr memcfga,r4 ; \
- addis r4,0,value@h ; \
- ori r4,r4,value@l ; \
- mtdcr memcfgd,r4 ;
+#if defined(CONFIG_DDR_ECC)
- .extern ecc_init
+#endif /* defined(CONFIG_DDR_ECC) */
.globl ext_bus_cntlr_init ext_bus_cntlr_init: +#if !defined(CFG_INIT_DCACHE_CS) #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
/*
* DDR2 setup
* DDR2 SDRAM Controller Setup
- /* Following the DDR Core Manual, here is the initialization */
- /* Step 1 */
- /* Step 2 */
- /* Step 3 */
- /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
- mtsdram_as(SDRAM_MB0CF, 0x00006701);
- /* SET SDRAM_MB1CF - Not enabled */
- mtsdram_as(SDRAM_MB1CF, 0x00000000);
- /* SET SDRAM_MB2CF - Not enabled */
- mtsdram_as(SDRAM_MB2CF, 0x00000000);
- /* SET SDRAM_MB3CF - Not enabled */
- mtsdram_as(SDRAM_MB3CF, 0x00000000);
- /* SDRAM_CLKTR: Adv Addr clock by 180 deg */
- mtsdram_as(SDRAM_CLKTR, 0x80000000);
- /* Refresh Time register (0x30) Refresh every 7.8125uS */
- mtsdram_as(SDRAM_RTR, 0x06180000);
- /* Set Memory Bank Configuration Registers */
- mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
Why do we now still have the SDRAM setup for Kilauea included in assembler? Is it because of the NAND booting support? If yes, then leave it as is and I'll clean this up later.
<snip>
diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c index 1d7a3fa..b7e2344 100644 --- a/board/amcc/kilauea/memory.c +++ b/board/amcc/kilauea/memory.c @@ -1,4 +1,7 @@ /*
- Copyright (c) 2008 Nuovation System Designs, LLC
- Grant Erickson gerickson@nuovations.com
- (C) Copyright 2007
- Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -30,10 +33,12 @@ void sdram_init(void) return; }
+#if defined(CONFIG_NAND_U_BOOT) long int initdram(int board_type) { return (CFG_MBYTES_SDRAM << 20); } +#endif /* defined(CONFIG_NAND_U_BOOT) */
#if defined(CFG_DRAM_TEST) int testdram (void) diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S index 5e9a5e0..4d0f460 100644 --- a/board/amcc/makalu/init.S +++ b/board/amcc/makalu/init.S @@ -1,8 +1,11 @@ /*
- Copyright (c) 2008 Nuovation System Designs, LLC
- Grant Erickson gerickson@nuovations.com
- (C) Copyright 2007-2008
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- Based on code provided from Senao and AMCC
- Originally based on code provided from Senao and AMCC
- See file CREDITS for list of people who contributed to this
- project.
@@ -23,126 +26,6 @@
- MA 02111-1307 USA
*/
-#include <config.h> -#include <ppc4xx.h>
-#include <ppc_asm.tmpl> -#include <ppc_defs.h>
-#define mtsdram_as(reg, value) \
- addi r4,0,reg ; \
- mtdcr memcfga,r4 ; \
- addis r4,0,value@h ; \
- ori r4,r4,value@l ; \
- mtdcr memcfgd,r4 ;
- .globl ext_bus_cntlr_init
ext_bus_cntlr_init:
- /*
* DDR2 setup*/- /* Following the DDR Core Manual, here is the initialization */
- /* Step 1 */
- /* Step 2 */
- /* Step 3 */
- /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
- mtsdram_as(SDRAM_MB0CF, 0x00005201);
- /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
- mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
- /* SDRAM_CLKTR: Adv Addr clock by 180 deg */
- mtsdram_as(SDRAM_CLKTR,0x80000000);
- /* Refresh Time register (0x30) Refresh every 7.8125uS */
- mtsdram_as(SDRAM_RTR, 0x06180000);
- /* SDRAM_SDTR1 */
- mtsdram_as(SDRAM_SDTR1, 0x80201000);
- /* SDRAM_SDTR2 */
- mtsdram_as(SDRAM_SDTR2, 0x32204232);
- /* SDRAM_SDTR3 */
- mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
- mtsdram_as(SDRAM_MMODE, 0x00000442);
- mtsdram_as(SDRAM_MEMODE, 0x00000404);
- /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
- mtsdram_as(SDRAM_MCOPT1, 0x04322000);
- /* NOP */
- mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
- /* precharge 3 DDR clock cycle */
- mtsdram_as(SDRAM_INITPLR1, 0x81900400);
- /* EMR2 twr = 2tck */
- mtsdram_as(SDRAM_INITPLR2, 0x81020000);
- /* EMR3 twr = 2tck */
- mtsdram_as(SDRAM_INITPLR3, 0x81030000);
- /* EMR DLL ENABLE twr = 2tck */
- mtsdram_as(SDRAM_INITPLR4, 0x81010404);
- /* MR w/ DLL reset
* Note: 5 is CL. May need to be changed*/- mtsdram_as(SDRAM_INITPLR5, 0x81000542);
- /* precharge 3 DDR clock cycle */
- mtsdram_as(SDRAM_INITPLR6, 0x81900400);
- /* Auto-refresh trfc = 26tck */
- mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
- /* Auto-refresh trfc = 26tck */
- mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
- /* Auto-refresh */
- mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
- /* Auto-refresh */
- mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
- /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
- mtsdram_as(SDRAM_INITPLR11, 0x81000442);
- mtsdram_as(SDRAM_INITPLR12, 0x81010780);
- mtsdram_as(SDRAM_INITPLR13, 0x81010400);
- mtsdram_as(SDRAM_INITPLR14, 0x00000000);
- mtsdram_as(SDRAM_INITPLR15, 0x00000000);
- /* SET MCIF0_CODT Die Termination On */
- mtsdram_as(SDRAM_CODT, 0x0080f837);
- mtsdram_as(SDRAM_MODT0, 0x01800000);
-#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
- mtsdram_as(SDRAM_MODT1, 0x00000000);
-#endif
- mtsdram_as(SDRAM_WRDTR, 0x00000000);
- /* SDRAM0_MCOPT2 (0X21) Start initialization */
- mtsdram_as(SDRAM_MCOPT2, 0x20000000);
- /* Step 5 */
- lis r3,0x1 /* 400000 = wait 100ms */
- mtctr r3
-pll_wait:
- bdnz pll_wait
- /* Step 6 */
- /* SDRAM_DLCR */
- mtsdram_as(SDRAM_DLCR, 0x030000a5);
- /* SDRAM_RDCC */
- mtsdram_as(SDRAM_RDCC, 0x40000000);
- /* SDRAM_RQDC */
- mtsdram_as(SDRAM_RQDC, 0x80000038);
- /* SDRAM_RFDC */
- mtsdram_as(SDRAM_RFDC, 0x00000209);
- /* Enable memory controller */
- mtsdram_as(SDRAM_MCOPT2, 0x28000000);
- blr
diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c index b03b60b..326feb7 100644 --- a/board/amcc/makalu/memory.c +++ b/board/amcc/makalu/memory.c
Please remove this file completely. It's not needed anymore, since we now use the common DDR2 controller init code you introduced with this patch. Please remove the testdram() function completely and move the sdram_init() to makalu.c.
Please fix if needed and resubmit. Thanks.
Best regards, Stefan
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