On Sun, 8 Mar 2020 22:05:42 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:
Hi Lukasz,
On 3/8/20 9:27 PM, Lukasz Majewski wrote:
On Wed, 26 Feb 2020 18:15:46 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:
mxsfb needs PLL5 as source, so let's setup it and set it as source for mxsfb(lcdif).
Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/clk/imx/clk-imxrt1050.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index e33d426363..2819ffb9ac 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -238,9 +238,9 @@ static int imxrt1050_clk_probe(struct udevice *dev) clk_dm(IMXRT1050_CLK_LCDIF, imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28)); -#ifdef CONFIG_SPL_BUILD struct clk *clk, *clk1;
+#ifdef CONFIG_SPL_BUILD /* bypass pll1 before setting its rate */ clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk); clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1); @@ -271,7 +271,18 @@ static int imxrt1050_clk_probe(struct udevice *dev) clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1); clk_set_parent(clk1, clk); +#else
/* Set PLL5 for LCDIF to its default 650Mhz */
clk_get_by_id(IMXRT1050_CLK_PLL5_VIDEO, &clk);
clk_enable(clk);
clk_set_rate(clk, 650000000UL);
clk_get_by_id(IMXRT1050_CLK_PLL5_BYPASS, &clk1);
clk_set_parent(clk1, clk);
/* Configure PLL5 as LCDIF source */
clk_get_by_id(IMXRT1050_CLK_LCDIF_SEL, &clk1);
clk_set_parent(clk1, clk);
As pointed by Fabio, this ^^^ should be substituted with a using assigned-parent-clocks in dts instead of being hardcoded here.
Upss.. Apparently I've missed the conversation. Thanks for pointing this out.
What do you think about it?
If it is relatively easy to do then I'm for it.
Thanks for reviewing and best regards
Best regards,
Lukasz Majewski
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