Add initial clock driver Allwinner for A31/A31s.
Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/Kconfig | 7 ++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a31.c | 130 ++++++++++++++++++++++++++++++++++++ 3 files changed, 138 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a31.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 6801b845cf..1f44fed2b9 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -22,6 +22,13 @@ config CLK_SUN5I_A10S This enables common clock driver support for platforms based on Allwinner A10s/A13 SoC.
+config CLK_SUN6I_A31 + bool "Clock driver for Allwinner A31/A31s" + default MACH_SUN6I + help + This enables common clock driver support for platforms based + on Allwinner A31/A31s SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index e217335a9b..e19aee9bf2 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o +obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c new file mode 100644 index 0000000000..3c8723c73c --- /dev/null +++ b/drivers/clk/sunxi/clk_a31.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <dt-bindings/clock/sun6i-a31-ccu.h> + +struct a31_clk_priv { + void *base; +}; + +static int a31_clk_enable(struct clk *clk) +{ + struct a31_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB1_OTG: + setbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_AHB1_EHCI0: + case CLK_AHB1_EHCI1: + setbits_le32(priv->base + 0x60, + BIT(26 + (clk->id - CLK_AHB1_EHCI0))); + return 0; + case CLK_AHB1_OHCI0: + case CLK_AHB1_OHCI1: + case CLK_AHB1_OHCI2: + setbits_le32(priv->base + 0x60, + BIT(29 + (clk->id - CLK_AHB1_OHCI0))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + setbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + setbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a31_clk_disable(struct clk *clk) +{ + struct a31_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB1_OTG: + clrbits_le32(priv->base + 0x60, BIT(24)); + return 0; + case CLK_AHB1_EHCI0: + case CLK_AHB1_EHCI1: + clrbits_le32(priv->base + 0x60, + BIT(26 + (clk->id - CLK_AHB1_EHCI0))); + return 0; + case CLK_AHB1_OHCI0: + case CLK_AHB1_OHCI1: + case CLK_AHB1_OHCI2: + clrbits_le32(priv->base + 0x60, + BIT(29 + (clk->id - CLK_AHB1_OHCI0))); + return 0; + case CLK_USB_PHY0: + case CLK_USB_PHY1: + case CLK_USB_PHY2: + clrbits_le32(priv->base + 0xcc, + BIT(8 + (clk->id - CLK_USB_PHY0))); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_OHCI2: + clrbits_le32(priv->base + 0xcc, + BIT(16 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a31_clk_ops = { + .enable = a31_clk_enable, + .disable = a31_clk_disable, +}; + +static int a31_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a31_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a31_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a31_clk_ids[] = { + { .compatible = "allwinner,sun6i-a31-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun6i_a31) = { + .name = "sun6i_a31_ccu", + .id = UCLASS_CLK, + .of_match = a31_clk_ids, + .priv_auto_alloc_size = sizeof(struct a31_clk_priv), + .ofdata_to_platdata = a31_clk_ofdata_to_platdata, + .ops = &a31_clk_ops, + .probe = a31_clk_probe, + .bind = sunxi_clk_bind, +};