This patch adds support for the Marvell Armada 38x SoC family.
Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash)
Tested on Marvell DB-88F6820-GP evaluation board.
Signed-off-by: Stefan Roese sr@denx.de Tested-by: Kevin Smith kevin.smith@elecsyscorp.com Tested-by: Dirk Eibach dirk.eibach@gdsys.cc
---
Changes in v3: None Changes in v2: - Made mvebu_soc_family() globally available so that it can be called from mbus.c - Add PL310 L2 cache base address
arch/arm/mach-mvebu/cpu.c | 73 ++++++++++++++++++++++++++-------- arch/arm/mach-mvebu/include/mach/cpu.h | 7 ++++ arch/arm/mach-mvebu/include/mach/soc.h | 9 +++++ 3 files changed, 73 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1cf70a9..eca5e21 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Stefan Roese sr@denx.de + * Copyright (C) 2014-2015 Stefan Roese sr@denx.de * * SPDX-License-Identifier: GPL-2.0+ */ @@ -40,6 +40,20 @@ void reset_cpu(unsigned long ignored) ; }
+int mvebu_soc_family(void) +{ + u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; + + if (devid == SOC_MV78460_ID) + return MVEBU_SOC_AXP; + + if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || + devid == SOC_88F6828_ID) + return MVEBU_SOC_A38X; + + return MVEBU_SOC_UNKNOWN; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -52,23 +66,48 @@ int print_cpuinfo(void) case SOC_MV78460_ID: puts("MV78460-"); break; - default: - puts("Unknown-"); + case SOC_88F6810_ID: + puts("MV88F6810-"); break; - } - - switch (revid) { - case 1: - puts("A0\n"); + case SOC_88F6820_ID: + puts("MV88F6820-"); break; - case 2: - puts("B0\n"); + case SOC_88F6828_ID: + puts("MV88F6828-"); break; default: - puts("??\n"); + puts("Unknown-"); break; }
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) { + switch (revid) { + case 1: + puts("A0\n"); + break; + case 2: + puts("B0\n"); + break; + default: + printf("?? (%x)\n", revid); + break; + } + } + + if (mvebu_soc_family() == MVEBU_SOC_A38X) { + switch (revid) { + case MV_88F68XX_Z1_ID: + puts("Z1\n"); + break; + case MV_88F68XX_A0_ID: + puts("A0\n"); + break; + default: + printf("?? (%x)\n", revid); + break; + } + } + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -145,11 +184,13 @@ int arch_cpu_init(void) */ mvebu_mbus_probe(NULL, 0);
- /* - * Now the SDRAM access windows can be reconfigured using - * the information in the SDRAM scratch pad registers - */ - update_sdram_window_sizes(); + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + /* + * Now the SDRAM access windows can be reconfigured using + * the information in the SDRAM scratch pad registers + */ + update_sdram_window_sizes(); + }
/* * Finally the mbus windows can be configured with the diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 297ac52..3b48460 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -56,6 +56,12 @@ enum cpu_attrib { CPU_ATTR_DEV_CS3 = 0x37, };
+enum { + MVEBU_SOC_AXP, + MVEBU_SOC_A38X, + MVEBU_SOC_UNKNOWN, +}; + /* * Default Device Address MAP BAR values */ @@ -106,6 +112,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_soc_family(void);
/* * Highspeed SERDES PHY config init, ported from bin_hdr diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index f3e0398..0a9307c 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -12,6 +12,13 @@ #define _MVEBU_SOC_H
#define SOC_MV78460_ID 0x7846 +#define SOC_88F6810_ID 0x6810 +#define SOC_88F6820_ID 0x6820 +#define SOC_88F6828_ID 0x6828 + +/* A38x revisions */ +#define MV_88F68XX_Z1_ID 0x0 +#define MV_88F68XX_A0_ID 0x4
/* TCLK Core Clock definition */ #ifndef CONFIG_SYS_TCLK @@ -25,6 +32,8 @@ #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) +#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) +#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) #define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))