Hello guys,
thanks a lot for your support. I've just retrieved Andrew's patch and I'll try to apply it in order to make loadb to work too.
Best regards, llandre
DAVE Electronics System House - R&D Department web: http://www.dave-tech.it email: r&d2@dave-tech.it
On 4/27/05, Kurt Stremerch kurt.stremerch@exys.be wrote:
- I tried to use both the "fpga load" and "fpga loadb" commands
respectively with the .bin and .bit files. The first one runs
succesfully
while the latter fails. In this case the header is parsed correctly but the FPGA is not programmed and the DONE does not go high.
The loadb function is a wrapper around the load function that converts your bitstream file first. Could you check what the difference is between your manually converted bitsteam file and the data that loadb creates? Imagine that the fpga startup clock configuration is set to the JTAG clock. Your conversion tool could change this automatically into the config clock. But the loadb doesn't make any change to your bitstream before the conversion takes place. This results in a successful configuration in "fpga load" but not in "fpga loadb".
I posted a patch to change the loadb command on Jan 11 (see the archives) that's not yet into cvs. Here's the issue:
- fixes a bug with the 'fpga loadb' command
The bug is in calculating the config data size - 4 bytes of length info were being read as signed chars, casted to long, shifted and added. The cast to long was doing sign extension and causing an incorrect result if a byte was greater than 0x80. For me this caused the fpga load to end early and time out waiting for the hardware completion.
There's some other stuff in the patch, too. I think the file has changed since I posted my patch, so there might be some breakage in applying it, but it's pretty simple and I'm sure you can do it by hand :-)