From: Tien Fong Chee tien.fong.chee@intel.com
Enables mailbox functionality for QSPI before initializing DDR, because storing calibration data into QSPI is required when DDR retention is enabled.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/mach-socfpga/spl_n5x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index c56b5a1b88..92037190e2 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -81,6 +81,12 @@ void board_init_f(ulong dummy) hang(); }
+ mbox_init(); + +#if IS_ENABLED(CONFIG_CADENCE_QSPI) + mbox_qspi_open(); +#endif + #if CONFIG_IS_ENABLED(ALTERA_SDRAM) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { @@ -88,10 +94,4 @@ void board_init_f(ulong dummy) hang(); } #endif - - mbox_init(); - -#ifdef CONFIG_CADENCE_QSPI - mbox_qspi_open(); -#endif }