Re: [PATCH] arm: allwinner: r40: update R40 DT files from linux 5.12-rc1

On Mon, 19 Apr 2021 12:30:57 +0300 Ivan Uvarov i.uvarov@cognitivepilot.com wrote:

Update R40 .dts{,i} and dt-binding headers to current version from kernel.

Files taken from Linux 5.12-rc1 release (commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8)

Signed-off-by: Ivan Uvarov i.uvarov@cognitivepilot.com

Looks good to me, thanks for the work! Can confirm the files are identical to the one from the latest kernel (5.12-rc8). Also boot tested my BananaPi M2 Berry and briefly tested SD card, SATA, USB and network, both in U-Boot and Linux (using that DT).

Reviewed-by: Andre Przywara andre.przywara@arm.com

Thanks, Andre

---

arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 23 +- arch/arm/dts/sun8i-r40.dtsi | 375 ++++++++++++++++-- arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 12 +- include/dt-bindings/clock/sun8i-r40-ccu.h | 6 +- .../interrupt-controller/arm-gic.h | 5 +- include/dt-bindings/thermal/thermal.h | 3 +- 6 files changed, 375 insertions(+), 49 deletions(-)

diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index c488aaacbd..a6a1087a0c 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -129,7 +129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>;

• phy-mode = "rgmii";

• phy-mode = "rgmii-id"; phy-supply = <&reg_dc1sw>; status = "okay";

}; @@ -164,6 +164,10 @@

#include "axp22x.dtsi"

+&ir0 {

• status = "okay";

+};

&mmc0 { vmmc-supply = <&reg_dcdc1>; bus-width = <4>; @@ -201,10 +205,15 @@ &pio { pinctrl-names = "default"; pinctrl-0 = <&clk_out_a_pin>;

• vcc-pa-supply = <&reg_aldo2>;
• vcc-pc-supply = <&reg_dcdc1>;
• vcc-pd-supply = <&reg_dcdc1>;
• vcc-pe-supply = <&reg_eldo1>;
• vcc-pf-supply = <&reg_dcdc1>;
• vcc-pg-supply = <&reg_dldo1>;

};

&reg_aldo2 {

• regulator-always-on; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-name = "vcc-pa";

@@ -218,16 +227,16 @@ };

&reg_dc1sw {

• regulator-min-microvolt = <3000000>;
• regulator-max-microvolt = <3000000>;

• regulator-min-microvolt = <3300000>;
• regulator-max-microvolt = <3300000>; regulator-name = "vcc-gmac-phy";

};

&reg_dcdc1 { regulator-always-on;

• regulator-min-microvolt = <3000000>;
• regulator-max-microvolt = <3000000>;
• regulator-name = "vcc-3v0";

• regulator-min-microvolt = <3300000>;
• regulator-max-microvolt = <3300000>;
• regulator-name = "vcc-3v3";

};

&reg_dcdc2 { diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 06b685869f..d5ad3b9efd 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -44,8 +44,10 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> +#include <dt-bindings/clock/sun8i-tcon-top.h> #include <dt-bindings/reset/sun8i-r40-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/thermal/thermal.h>

/ { #address-cells = <1>; @@ -78,25 +80,25 @@ #address-cells = <1>; #size-cells = <0>;

• cpu@0 {
  

• cpu0: cpu@0 {
  compatible = "arm,cortex-a7";
  device_type = "cpu";
  reg = <0>;
  

  };

• cpu@1 {
  

• cpu1: cpu@1 {
  compatible = "arm,cortex-a7";
  device_type = "cpu";
  reg = <1>;
  

  };

• cpu@2 {
  

• cpu2: cpu@2 {
  compatible = "arm,cortex-a7";
  device_type = "cpu";
  reg = <2>;
  

  };

• cpu@3 {
  

• cpu3: cpu@3 {
  compatible = "arm,cortex-a7";
  device_type = "cpu";
  reg = <3>;
  

@@ -109,6 +111,22 @@ status = "disabled"; };

• thermal-zones {

• cpu_thermal: cpu0-thermal {
  

• 	/* milliseconds */
  

• 	polling-delay-passive = <0>;
  

• 	polling-delay = <0>;
  

• 	thermal-sensors = <&ths 0>;
  

• };
  

• gpu_thermal: gpu-thermal {
  

• 	/* milliseconds */
  

• 	polling-delay-passive = <0>;
  

• 	polling-delay = <0>;
  

• 	thermal-sensors = <&ths 1>;
  

• };
  

• };
• soc { compatible = "simple-bus"; #address-cells = <1>;

@@ -118,11 +136,11 @@ display_clocks: clock@1000000 { compatible = "allwinner,sun8i-r40-de2-clk", "allwinner,sun8i-h3-de2-clk";

• 	reg = <0x01000000 0x100000>;
  

• 	clocks = <&ccu CLK_DE>,
  

• 		 <&ccu CLK_BUS_DE>;
  

• 	clock-names = "mod",
  

• 		      "bus";
  

• 	reg = <0x01000000 0x10000>;
  

• 	clocks = <&ccu CLK_BUS_DE>,
  

• 		 <&ccu CLK_DE>;
  

• 	clock-names = "bus",
  

• 		      "mod";
  resets = <&ccu RST_BUS_DE>;
  #clock-cells = <1>;
  #reset-cells = <1>;
  

@@ -172,6 +190,48 @@ }; };

• deinterlace: deinterlace@1400000 {
  

• 	compatible =
  

"allwinner,sun8i-r40-deinterlace",

"allwinner,sun8i-h3-deinterlace";

• 	reg = <0x01400000 0x20000>;
  

• 	clocks = <&ccu CLK_BUS_DEINTERLACE>,
  

• 		 <&ccu CLK_DEINTERLACE>,
  

• 		 /*
  

• 		  * NOTE: Contrary to what datasheet
  

claims,

• 		  * DRAM deinterlace gate doesn't
  

exist and

• 		  * it's shared with CSI1.
  

• 		  */
  

• 		 <&ccu CLK_DRAM_CSI1>;
  

• 	clock-names = "bus", "mod", "ram";
  

• 	resets = <&ccu RST_BUS_DEINTERLACE>;
  

• 	interrupts = <GIC_SPI 93
  

IRQ_TYPE_LEVEL_HIGH>;

• 	interconnects = <&mbus 9>;
  

• 	interconnect-names = "dma-mem";
  

• };
  

• syscon: system-control@1c00000 {
  

• 	compatible =
  

"allwinner,sun8i-r40-system-control",

"allwinner,sun4i-a10-system-control";

• 	reg = <0x01c00000 0x30>;
  

• 	#address-cells = <1>;
  

• 	#size-cells = <1>;
  

• 	ranges;
  

• 	sram_c: sram@1d00000 {
  

• 		compatible = "mmio-sram";
  

• 		reg = <0x01d00000 0xd0000>;
  

• 		#address-cells = <1>;
  

• 		#size-cells = <1>;
  

• 		ranges = <0 0x01d00000 0xd0000>;
  

• 		ve_sram: sram-section@0 {
  

• 			compatible =
  

"allwinner,sun8i-r40-sram-c1",

"allwinner,sun4i-a10-sram-c1";

• 			reg = <0x000000 0x80000>;
  

• 		};
  

• 	};
  

• };
  

• nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller;

@@ -180,6 +240,69 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; };

• dma: dma-controller@1c02000 {
  

• 	compatible = "allwinner,sun8i-r40-dma",
  

• 		     "allwinner,sun50i-a64-dma";
  

• 	reg = <0x01c02000 0x1000>;
  

• 	interrupts = <GIC_SPI 27
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_DMA>;
  

• 	dma-channels = <16>;
  

• 	dma-requests = <31>;
  

• 	resets = <&ccu RST_BUS_DMA>;
  

• 	#dma-cells = <1>;
  

• };
  

• spi0: spi@1c05000 {
  

• 	compatible = "allwinner,sun8i-r40-spi",
  

• 		     "allwinner,sun8i-h3-spi";
  

• 	reg = <0x01c05000 0x1000>;
  

• 	interrupts = <GIC_SPI 10
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_SPI0>, <&ccu
  

CLK_SPI0>;

• 	clock-names = "ahb", "mod";
  

• 	resets = <&ccu RST_BUS_SPI0>;
  

• 	status = "disabled";
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• };
  

• spi1: spi@1c06000 {
  

• 	compatible = "allwinner,sun8i-r40-spi",
  

• 		     "allwinner,sun8i-h3-spi";
  

• 	reg = <0x01c06000 0x1000>;
  

• 	interrupts = <GIC_SPI 11
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_SPI1>, <&ccu
  

CLK_SPI1>;

• 	clock-names = "ahb", "mod";
  

• 	resets = <&ccu RST_BUS_SPI1>;
  

• 	status = "disabled";
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• };
  

• csi0: csi@1c09000 {
  

• 	compatible = "allwinner,sun8i-r40-csi0",
  

• 		     "allwinner,sun7i-a20-csi0";
  

• 	reg = <0x01c09000 0x1000>;
  

• 	interrupts = <GIC_SPI 42
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_CSI0>, <&ccu
  

CLK_CSI_SCLK>,

• 		 <&ccu CLK_DRAM_CSI0>;
  

• 	clock-names = "bus", "isp", "ram";
  

• 	resets = <&ccu RST_BUS_CSI0>;
  

• 	interconnects = <&mbus 5>;
  

• 	interconnect-names = "dma-mem";
  

• 	status = "disabled";
  

• };
  

• video-codec@1c0e000 {
  

• 	compatible =
  

"allwinner,sun8i-r40-video-engine";

• 	reg = <0x01c0e000 0x1000>;
  

• 	clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
  

• 	<&ccu CLK_DRAM_VE>;
  

• 	clock-names = "ahb", "mod", "ram";
  

• 	resets = <&ccu RST_BUS_VE>;
  

• 	interrupts = <GIC_SPI 53
  

IRQ_TYPE_LEVEL_HIGH>;

• 	allwinner,sram = <&ve_sram 1>;
  

• };
  

• mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-r40-mmc", "allwinner,sun50i-a64-mmc";

@@ -266,6 +389,38 @@ #phy-cells = <1>; };

• crypto: crypto@1c15000 {
  

• 	compatible = "allwinner,sun8i-r40-crypto";
  

• 	reg = <0x01c15000 0x1000>;
  

• 	interrupts = <GIC_SPI 94
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
  

• 	clock-names = "bus", "mod";
  

• 	resets = <&ccu RST_BUS_CE>;
  

• };
  

• spi2: spi@1c17000 {
  

• 	compatible = "allwinner,sun8i-r40-spi",
  

• 		     "allwinner,sun8i-h3-spi";
  

• 	reg = <0x01c17000 0x1000>;
  

• 	interrupts = <GIC_SPI 12
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_SPI2>, <&ccu
  

CLK_SPI2>;

• 	clock-names = "ahb", "mod";
  

• 	resets = <&ccu RST_BUS_SPI2>;
  

• 	status = "disabled";
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• };
  

• ahci: sata@1c18000 {
  

• 	compatible = "allwinner,sun8i-r40-ahci";
  

• 	reg = <0x01c18000 0x1000>;
  

• 	interrupts = <GIC_SPI 56
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_SATA>, <&ccu
  

CLK_SATA>;

• 	resets = <&ccu RST_BUS_SATA>;
  

• 	reset-names = "ahci";
  

• 	status = "disabled";
  

• };
  

• ehci1: usb@1c19000 { compatible = "allwinner,sun8i-r40-ehci",

"generic-ehci"; reg = <0x01c19000 0x100>; @@ -312,6 +467,19 @@ status = "disabled"; };

• spi3: spi@1c1f000 {
  

• 	compatible = "allwinner,sun8i-r40-spi",
  

• 		     "allwinner,sun8i-h3-spi";
  

• 	reg = <0x01c1f000 0x1000>;
  

• 	interrupts = <GIC_SPI 50
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_SPI3>, <&ccu
  

CLK_SPI3>;

• 	clock-names = "ahb", "mod";
  

• 	resets = <&ccu RST_BUS_SPI3>;
  

• 	status = "disabled";
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• };
  

• ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>;

@@ -322,8 +490,7 @@ };

rtc: rtc@1c20400 {

• 	compatible = "allwinner,sun8i-r40-rtc",
  

• 		     "allwinner,sun8i-h3-rtc";
  

• 	compatible = "allwinner,sun8i-r40-rtc";
  reg = <0x01c20400 0x400>;
  interrupts = <GIC_SPI 24
  

IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out"; @@ -347,6 +514,20 @@ function = "clk_out_a"; };

• 	/omit-if-no-ref/
  

• 	csi0_8bits_pins: csi0-8bits-pins {
  

• 		pins = "PE0", "PE2", "PE3", "PE4",
  

"PE5",

• 		       "PE6", "PE7", "PE8", "PE9",
  

"PE10",

• 		       "PE11";
  

• 		function = "csi0";
  

• 	};
  

• 	/omit-if-no-ref/
  

• 	csi0_mclk_pin: csi0-mclk-pin {
  

• 		pins = "PE1";
  

• 		function = "csi0";
  

• 	};
  

• gmac_rgmii_pins: gmac-rgmii-pins {
  	pins = "PA0", "PA1", "PA2", "PA3",
  	       "PA4", "PA5", "PA6", "PA7",
  

@@ -365,6 +546,36 @@ function = "i2c0"; };

• 	i2c1_pins: i2c1-pins {
  

• 		pins = "PB18", "PB19";
  

• 		function = "i2c1";
  

• 	};
  

• 	i2c2_pins: i2c2-pins {
  

• 		pins = "PB20", "PB21";
  

• 		function = "i2c2";
  

• 	};
  

• 	i2c3_pins: i2c3-pins {
  

• 		pins = "PI0", "PI1";
  

• 		function = "i2c3";
  

• 	};
  

• 	i2c4_pins: i2c4-pins {
  

• 		pins = "PI2", "PI3";
  

• 		function = "i2c4";
  

• 	};
  

• 	ir0_pins: ir0-pins {
  

• 		pins = "PB4";
  

• 		function = "ir0";
  

• 	};
  

• 	ir1_pins: ir1-pins {
  

• 		pins = "PB23";
  

• 		function = "ir1";
  

• 	};
  

• mmc0_pins: mmc0-pins {
  	pins = "PF0", "PF1", "PF2",
  	       "PF3", "PF4", "PF5";
  

@@ -390,6 +601,36 @@ bias-pull-up; };

• 	/omit-if-no-ref/
  

• 	spi0_pc_pins: spi0-pc-pins {
  

• 		pins = "PC0", "PC1", "PC2";
  

• 		function = "spi0";
  

• 	};
  

• 	/omit-if-no-ref/
  

• 	spi0_cs0_pc_pin: spi0-cs0-pc-pin {
  

• 		pins = "PC23";
  

• 		function = "spi0";
  

• 	};
  

• 	/omit-if-no-ref/
  

• 	spi1_pi_pins: spi1-pi-pins {
  

• 		pins = "PI17", "PI18", "PI19";
  

• 		function = "spi1";
  

• 	};
  

• 	/omit-if-no-ref/
  

• 	spi1_cs0_pi_pin: spi1-cs0-pi-pin {
  

• 		pins = "PI16";
  

• 		function = "spi1";
  

• 	};
  

• 	/omit-if-no-ref/
  

• 	spi1_cs1_pi_pin: spi1-cs1-pi-pin {
  

• 		pins = "PI15";
  

• 		function = "spi1";
  

• 	};
  

• uart0_pb_pins: uart0-pb-pins {
  	pins = "PB22", "PB23";
  	function = "uart0";
  

@@ -409,6 +650,45 @@ wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>;

• 	interrupts = <GIC_SPI 24
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&osc24M>;
  

• };
  

• ir0: ir@1c21800 {
  

• 	compatible = "allwinner,sun8i-r40-ir",
  

• 		     "allwinner,sun6i-a31-ir";
  

• 	reg = <0x01c21800 0x400>;
  

• 	pinctrl-0 = <&ir0_pins>;
  

• 	pinctrl-names = "default";
  

• 	clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
  

• 	clock-names = "apb", "ir";
  

• 	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  

• 	resets = <&ccu RST_BUS_IR0>;
  

• 	status = "disabled";
  

• };
  

• ir1: ir@1c21c00 {
  

• 	compatible = "allwinner,sun8i-r40-ir",
  

• 		     "allwinner,sun6i-a31-ir";
  

• 	reg = <0x01c21c00 0x400>;
  

• 	pinctrl-0 = <&ir1_pins>;
  

• 	pinctrl-names = "default";
  

• 	clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
  

• 	clock-names = "apb", "ir";
  

• 	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  

• 	resets = <&ccu RST_BUS_IR1>;
  

• 	status = "disabled";
  

• };
  

• ths: thermal-sensor@1c24c00 {
  

• 	compatible = "allwinner,sun8i-r40-ths";
  

• 	reg = <0x01c24c00 0x100>;
  

• 	clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
  

• 	clock-names = "bus", "mod";
  

• 	interrupts = <GIC_SPI 36
  

IRQ_TYPE_LEVEL_HIGH>;

• 	resets = <&ccu RST_BUS_THS>;
  

• 	/* TODO: add nvmem-cells for calibration */
  

• 	#thermal-sensor-cells = <1>;
  

  };

  uart0: serial@1c28000 {

@@ -518,6 +798,8 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>;

• 	pinctrl-0 = <&i2c1_pins>;
  

• 	pinctrl-names = "default";
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <0>;
  

@@ -529,6 +811,8 @@ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>;

• 	pinctrl-0 = <&i2c2_pins>;
  

• 	pinctrl-names = "default";
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <0>;
  

@@ -540,6 +824,8 @@ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>;

• 	pinctrl-0 = <&i2c3_pins>;
  

• 	pinctrl-names = "default";
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <0>;
  

@@ -551,22 +837,33 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C4>; resets = <&ccu RST_BUS_I2C4>;

• 	pinctrl-0 = <&i2c4_pins>;
  

• 	pinctrl-names = "default";
  status = "disabled";
  #address-cells = <1>;
  #size-cells = <0>;
  

  };

• ahci: sata@1c18000 {
  

• 	compatible = "allwinner,sun8i-r40-ahci";
  

• 	reg = <0x01c18000 0x1000>;
  

• 	interrupts = <GIC_SPI 56
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_SATA>, <&ccu
  

CLK_SATA>;

• 	resets = <&ccu RST_BUS_SATA>;
  

• 	resets-name = "ahci";
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• 	status = "disabled";
  

• mali: gpu@1c40000 {
  

• 	compatible = "allwinner,sun8i-r40-mali",
  

"arm,mali-400";

• 	reg = <0x01c40000 0x10000>;
  

• 	interrupts = <GIC_SPI 69
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 70
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 71
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 72
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 74
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 75
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 73
  

IRQ_TYPE_LEVEL_HIGH>;

• 	interrupt-names = "gp",
  

• 			  "gpmmu",
  

• 			  "pp0",
  

• 			  "ppmmu0",
  

• 			  "pp1",
  

• 			  "ppmmu1",
  

• 			  "pmu";
  

• 	clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
  

• 	clock-names = "bus", "core";
  

• 	resets = <&ccu RST_BUS_GPU>;
  

  };

  gmac: ethernet@1c50000 {

@@ -588,6 +885,16 @@ }; };

• mbus: dram-controller@1c62000 {
  

• 	compatible = "allwinner,sun8i-r40-mbus";
  

• 	reg = <0x01c62000 0x1000>;
  

• 	clocks = <&ccu 155>;
  

• 	#address-cells = <1>;
  

• 	#size-cells = <1>;
  

• 	dma-ranges = <0x00000000 0x40000000
  

0x80000000>;

• 	#interconnect-cells = <1>;
  

• };
  

• tcon_top: tcon-top@1c70000 { compatible = "allwinner,sun8i-r40-tcon-top"; reg = <0x01c70000 0x1000>;

@@ -614,12 +921,9 @@ #size-cells = <0>;

		tcon_top_mixer0_in: port@0 {

• 			#address-cells = <1>;
  

• 			#size-cells = <0>;
  		reg = <0>;
  
  

• 			tcon_top_mixer0_in_mixer0:
  

endpoint@0 {

• 				reg = <0>;
  

• 			tcon_top_mixer0_in_mixer0:
  

endpoint { remote-endpoint = <&mixer0_out_tcon_top>; }; }; @@ -713,7 +1017,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top
  

0>;

• 	clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top
  

CLK_TCON_TOP_TV0>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV0>; reset-names = "lcd"; @@ -756,7 +1060,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c74000 0x1000>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top
  

1>;

• 	clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top
  

CLK_TCON_TOP_TV1>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV1>; reset-names = "lcd"; @@ -798,7 +1102,7 @@ gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>,

• 	      <0x01c82000 0x1000>,
  

• 	      <0x01c82000 0x2000>,
        <0x01c84000 0x2000>,
        <0x01c86000 0x2000>;
  interrupt-controller;
  

@@ -818,7 +1122,7 @@ resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>;

• 	phy-names = "hdmi-phy";
  

• 	phy-names = "phy";
  status = "disabled";
  
  ports {
  

@@ -843,7 +1147,7 @@ compatible = "allwinner,sun8i-r40-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,

• 		 <&ccu 7>, <&ccu 16>;
  

• 		 <&ccu CLK_PLL_VIDEO0>, <&ccu
  

CLK_PLL_VIDEO1>; clock-names = "bus", "mod", "pll-0", "pll-1"; resets = <&ccu RST_BUS_HDMI0>; reset-names = "phy"; @@ -851,6 +1155,15 @@ }; };

• pmu {

• compatible = "arm,cortex-a7-pmu";
  

• interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  

• 	     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  

• 	     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  

• 	     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
  

• interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
  

<&cpu3>;

• };
• timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |

IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts index 15c22b06fc..47954551f5 100644 --- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts @@ -120,7 +120,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>;

• phy-mode = "rgmii";

• phy-mode = "rgmii-id"; phy-supply = <&reg_dc1sw>; status = "okay";

}; @@ -198,16 +198,16 @@ };

&reg_dc1sw {

• regulator-min-microvolt = <3000000>;
• regulator-max-microvolt = <3000000>;

• regulator-min-microvolt = <3300000>;
• regulator-max-microvolt = <3300000>; regulator-name = "vcc-gmac-phy";

};

&reg_dcdc1 { regulator-always-on;

• regulator-min-microvolt = <3000000>;
• regulator-max-microvolt = <3000000>;
• regulator-name = "vcc-3v0";

• regulator-min-microvolt = <3300000>;
• regulator-max-microvolt = <3300000>;
• regulator-name = "vcc-3v3";

};

&reg_dcdc2 { diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h index 4fa5f69fc2..d7337b55a4 100644 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ b/include/dt-bindings/clock/sun8i-r40-ccu.h @@ -43,6 +43,10 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ #define _DT_BINDINGS_CLK_SUN8I_R40_H_

+#define CLK_PLL_VIDEO0 7

+#define CLK_PLL_VIDEO1 16

#define CLK_CPU 24

#define CLK_BUS_MIPI_DSI 29 @@ -172,7 +176,7 @@ #define CLK_AVS 152 #define CLK_HDMI 153 #define CLK_HDMI_SLOW 154

+#define CLK_MBUS 155 #define CLK_DSI_DPHY 156 #define CLK_TVE0 157 #define CLK_TVE1 158 diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index 1ea1b702fe..35b6f69b7d 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /*

• This header provides constants for the ARM GIC.

*/ @@ -7,14 +8,14 @@

#include <dt-bindings/interrupt-controller/irq.h>

-/* interrupt specific cell 0 */ +/* interrupt specifier cell 0 */

#define GIC_SPI 0 #define GIC_PPI 1

/*

• Interrupt specifier cell 2.

• • The flaggs in irq.h are valid, plus those below.

• • The flags in irq.h are valid, plus those below.
  */

#define GIC_CPU_MASK_RAW(x) ((x) << 8) #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h index b5e6b0069a..bc7babb1a6 100644 --- a/include/dt-bindings/thermal/thermal.h +++ b/include/dt-bindings/thermal/thermal.h @@ -1,10 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /*

• This header provides constants for most thermal bindings.
• Copyright (C) 2013 Texas Instruments
• Eduardo Valentin eduardo.valentin@ti.com

• • GPLv2 only
  */

#ifndef _DT_BINDINGS_THERMAL_THERMAL_H