On Wed, Jul 07, 2021 at 12:02:05AM +0800, Leo Liang wrote:
Hi Tom,
The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de:
Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829:
board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081
Please note: w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #address-cells (1) differs from / (2) w+(openpiton_riscv64 openpiton_riscv64_spl) arch/riscv/dts/openpiton-riscv64.dtb: Warning (ranges_format): /soc:ranges: empty "ranges" property but its #size-cells (1) differs from / (2)
need to be fixed in a follow up PR (and the relevant dts files should be added to the board MAINTAINER file too). That said, applied to u-boot/master, thanks!